kit_de2.fit.qmsg

VGA sourcecodes/documents

{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clock  " "Info: Automatically promoted node clock " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "VGA_CLK " "Info: Destination node VGA_CLK" {  } { { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 42 -1 0 } } { "e:/chuong_trinh/quartusii/win/Assignment Editor.qase" "" { Assignment "e:/chuong_trinh/quartusii/win/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "" { VGA_CLK } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "" { VGA_CLK } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clock~3 " "Info: Destination node clock~3" {  } { { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 52 -1 0 } } { "e:/chuong_trinh/quartusii/win/Assignment Editor.qase" "" { Assignment "e:/chuong_trinh/quartusii/win/Assignment Editor.qase" 1 { { 0 "clock~3" } } } } { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "" { clock~3 } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "" { clock~3 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 52 -1 0 } } { "e:/chuong_trinh/quartusii/win/Assignment Editor.qase" "" { Assignment "e:/chuong_trinh/quartusii/win/Assignment Editor.qase" 1 { { 0 "clock" } } } } { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}