kit_de2.map.qmsg

VGA sourcecodes/documents

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_4oa vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|decode_4oa:decode3 " "Info: Elaborating entity \"decode_4oa\" for hierarchy \"vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|decode_4oa:decode3\"" {  } { { "db/altsyncram_4qc1.tdf" "decode3" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/altsyncram_4qc1.tdf" 50 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_4oa vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|decode_4oa:deep_decode " "Info: Elaborating entity \"decode_4oa\" for hierarchy \"vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|decode_4oa:deep_decode\"" {  } { { "db/altsyncram_4qc1.tdf" "deep_decode" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/altsyncram_4qc1.tdf" 51 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_kib.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_kib.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_kib " "Info: Found entity 1: mux_kib" {  } { { "db/mux_kib.tdf" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/mux_kib.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_kib vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|mux_kib:mux2 " "Info: Elaborating entity \"mux_kib\" for hierarchy \"vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|mux_kib:mux2\"" {  } { { "db/altsyncram_4qc1.tdf" "mux2" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/altsyncram_4qc1.tdf" 52 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga_sync vga_controller:BLOCK2\|vga_sync:VGA_khoi2 " "Info: Elaborating entity \"vga_sync\" for hierarchy \"vga_controller:BLOCK2\|vga_sync:VGA_khoi2\"" {  } { { "vga_controller.v" "VGA_khoi2" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/vga_controller.v" 70 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "D_FFs vga_controller:BLOCK2\|vga_sync:VGA_khoi2\|D_FFs:V1 " "Info: Elaborating entity \"D_FFs\" for hierarchy \"vga_controller:BLOCK2\|vga_sync:VGA_khoi2\|D_FFs:V1\"" {  } { { "vga_sync.v" "V1" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/vga_sync.v" 41 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Khoi_phat_hien_canh_len vga_controller:BLOCK2\|Khoi_phat_hien_canh_len:VGA_CONTROLLER " "Info: Elaborating entity \"Khoi_phat_hien_canh_len\" for hierarchy \"vga_controller:BLOCK2\|Khoi_phat_hien_canh_len:VGA_CONTROLLER\"" {  } { { "vga_controller.v" "VGA_CONTROLLER" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/vga_controller.v" 128 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SRAM_interface SRAM_interface:BLOCK3 " "Info: Elaborating entity \"SRAM_interface\" for hierarchy \"SRAM_interface:BLOCK3\"" {  } { { "kit_DE2.v" "BLOCK3" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 105 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "control_wr_rd_for_SRAM control_wr_rd_for_SRAM:BLOCK4 " "Info: Elaborating entity \"control_wr_rd_for_SRAM\" for hierarchy \"control_wr_rd_for_SRAM:BLOCK4\"" {  } { { "kit_DE2.v" "BLOCK4" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 132 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Khoi_FIFO Khoi_FIFO:BLOCK_5 " "Info: Elaborating entity \"Khoi_FIFO\" for hierarchy \"Khoi_FIFO:BLOCK_5\"" {  } { { "kit_DE2.v" "BLOCK_5" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 167 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FIFO_Image Khoi_FIFO:BLOCK_5\|FIFO_Image:BLOCK_FIFO_0 " "Info: Elaborating entity \"FIFO_Image\" for hierarchy \"Khoi_FIFO:BLOCK_5\|FIFO_Image:BLOCK_FIFO_0\"" {  } { { "Khoi_FIFO.v" "BLOCK_FIFO_0" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/Khoi_FIFO.v" 57 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/chuong_trinh/quartusii/libraries/megafunctions/scfifo.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/chuong_trinh/quartusii/libraries/megafunctions/scfifo.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo " "Info: Found entity 1: scfifo" {  } { { "scfifo.tdf" "" { Text "e:/chuong_trinh/quartusii/libraries/megafunctions/scfifo.tdf" 234 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo Khoi_FIFO:BLOCK_5\|FIFO_Image:BLOCK_FIFO_0\|scfifo:scfifo_component " "Info: Elaborating entity \"scfifo\" for hierarchy \"Khoi_FIFO:BLOCK_5\|FIFO_Image:BLOCK_FIFO_0\|scfifo:scfifo_component\"" {  } { { "FIFO_Image.v" "scfifo_component" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/FIFO_Image.v" 68 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "Khoi_FIFO:BLOCK_5\|FIFO_Image:BLOCK_FIFO_0\|scfifo:scfifo_component " "Info: Elaborated megafunction instantiation \"Khoi_FIFO:BLOCK_5\|FIFO_Image:BLOCK_FIFO_0\|scfifo:scfifo_component\"" {  } { { "FIFO_Image.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/FIFO_Image.v" 68 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_1eu.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/scfifo_1eu.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_1eu " "Info: Found entity 1: scfifo_1eu" {  } { { "db/scfifo_1eu.tdf" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/scfifo_1eu.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_1eu Khoi_FIFO:BLOCK_5\|FIFO_Image:BLOCK_FIFO_0\|scfifo:scfifo_component\|scfifo_1eu:auto_generated " "Info: Elaborating entity \"scfifo_1eu\" for hierarchy \"Khoi_FIFO:BLOCK_5\|FIFO_Image:BLOCK_FIFO_0\|scfifo:scfifo_component\|scfifo_1eu:auto_generated\"" {  } { { "scfifo.tdf" "auto_generated" { Text "e:/chuong_trinh/quartusii/libraries/megafunctions/scfifo.tdf" 294 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_8ku.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_8ku.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_8ku " "Info: Found entity 1: a_dpfifo_8ku" {  } { { "db/a_dpfifo_8ku.tdf" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/a_dpfifo_8ku.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_8ku Khoi_FIFO:BLOCK_5\|FIFO_Image:BLOCK_FIFO_0\|scfifo:scfifo_component\|scfifo_1eu:auto_generated\|a_dpfifo_8ku:dpfifo " "Info: Elaborating entity \"a_dpfifo_8ku\" for hierarchy \"Khoi_FIFO:BLOCK_5\|FIFO_Image:BLOCK_FIFO_0\|scfifo:scfifo_component\|scfifo_1eu:auto_generated\|a_dpfifo_8ku:dpfifo\"" {  } { { "db/scfifo_1eu.tdf" "dpfifo" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/scfifo_1eu.tdf" 33 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_u7e.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_u7e.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_u7e " "Info: Found entity 1: a_fefifo_u7e" {  } { { "db/a_fefifo_u7e.tdf" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/a_fefifo_u7e.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_u7e Khoi_FIFO:BLOCK_5\|FIFO_Image:BLOCK_FIFO_0\|scfifo:scfifo_component\|scfifo_1eu:auto_generated\|a_dpfifo_8ku:dpfifo\|a_fefifo_u7e:fifo_state " "Info: Elaborating entity \"a_fefifo_u7e\" for hierarchy \"Khoi_FIFO:BLOCK_5\|FIFO_Image:BLOCK_FIFO_0\|scfifo:scfifo_component\|scfifo_1eu:auto_generated\|a_dpfifo_8ku:dpfifo\|a_fefifo_u7e:fifo_state\"" {  } { { "db/a_dpfifo_8ku.tdf" "fifo_state" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/a_dpfifo_8ku.tdf" 38 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_sj7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_sj7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_sj7 " "Info: Found entity 1: cntr_sj7" {  } { { "db/cntr_sj7.tdf" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/cntr_sj7.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_sj7 Khoi_FIFO:BLOCK_5\|FIFO_Image:BLOCK_FIFO_0\|scfifo:scfifo_component\|scfifo_1eu:auto_generated\|a_dpfifo_8ku:dpfifo\|a_fefifo_u7e:fifo_state\|cntr_sj7:count_usedw " "Info: Elaborating entity \"cntr_sj7\" for hierarchy \"Khoi_FIFO:BLOCK_5\|FIFO_Image:BLOCK_FIFO_0\|scfifo:scfifo_component\|scfifo_1eu:auto_generated\|a_dpfifo_8ku:dpfifo\|a_fefifo_u7e:fifo_state\|cntr_sj7:count_usedw\"" {  } { { "db/a_fefifo_u7e.tdf" "count_usedw" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/a_fefifo_u7e.tdf" 37 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_4it.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/dpram_4it.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_4it " "Info: Found entity 1: dpram_4it" {  } { { "db/dpram_4it.tdf" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/dpram_4it.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_4it Khoi_FIFO:BLOCK_5\|FIFO_Image:BLOCK_FIFO_0\|scfifo:scfifo_component\|scfifo_1eu:auto_generated\|a_dpfifo_8ku:dpfifo\|dpram_4it:FIFOram " "Info: Elaborating entity \"dpram_4it\" for hierarchy \"Khoi_FIFO:BLOCK_5\|FIFO_Image:BLOCK_FIFO_0\|scfifo:scfifo_component\|scfifo_1eu:auto_generated\|a_dpfifo_8ku:dpfifo\|dpram_4it:FIFOram\"" {  } { { "db/a_dpfifo_8ku.tdf" "FIFOram" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/a_dpfifo_8ku.tdf" 39 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_6sj1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_6sj1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_6sj1 " "Info: Found entity 1: altsyncram_6sj1" {  } { { "db/altsyncram_6sj1.tdf" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/altsyncram_6sj1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}