kit_de2.tan.qmsg

VGA sourcecodes/documents

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLOCK_50 " "Info: Assuming node \"CLOCK_50\" is an undefined clock" {  } { { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 26 -1 0 } } { "e:/chuong_trinh/quartusii/win/Assignment Editor.qase" "" { Assignment "e:/chuong_trinh/quartusii/win/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clock " "Info: Detected ripple clock \"clock\" as buffer" {  } { { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 52 -1 0 } } { "e:/chuong_trinh/quartusii/win/Assignment Editor.qase" "" { Assignment "e:/chuong_trinh/quartusii/win/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLOCK_50 register memory control_wr_rd_for_SRAM:BLOCK4\|wr_address\[12\] vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|ram_block1a6~porta_we_reg 200.0 MHz Internal " "Info: Clock \"CLOCK_50\" Internal fmax is restricted to 200.0 MHz between source register \"control_wr_rd_for_SRAM:BLOCK4\|wr_address\[12\]\" and destination memory \"vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|ram_block1a6~porta_we_reg\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.522 ns + Longest register memory " "Info: + Longest register to memory delay is 4.522 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns control_wr_rd_for_SRAM:BLOCK4\|wr_address\[12\] 1 REG LCFF_X28_Y10_N21 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X28_Y10_N21; Fanout = 6; REG Node = 'control_wr_rd_for_SRAM:BLOCK4\|wr_address\[12\]'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "" { control_wr_rd_for_SRAM:BLOCK4|wr_address[12] } "NODE_NAME" } } { "control_wr_rd_for_SRAM.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/control_wr_rd_for_SRAM.v" 204 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.438 ns) 1.212 ns vga_controller:BLOCK2\|address\[12\]~142 2 COMB LCCOMB_X27_Y10_N10 4 " "Info: 2: + IC(0.774 ns) + CELL(0.438 ns) = 1.212 ns; Loc. = LCCOMB_X27_Y10_N10; Fanout = 4; COMB Node = 'vga_controller:BLOCK2\|address\[12\]~142'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "1.212 ns" { control_wr_rd_for_SRAM:BLOCK4|wr_address[12] vga_controller:BLOCK2|address[12]~142 } "NODE_NAME" } } { "vga_controller.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/vga_controller.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.446 ns) + CELL(0.150 ns) 1.808 ns vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|decode_4oa:deep_decode\|w_anode231w\[2\] 3 COMB LCCOMB_X28_Y10_N12 112 " "Info: 3: + IC(0.446 ns) + CELL(0.150 ns) = 1.808 ns; Loc. = LCCOMB_X28_Y10_N12; Fanout = 112; COMB Node = 'vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|decode_4oa:deep_decode\|w_anode231w\[2\]'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "0.596 ns" { vga_controller:BLOCK2|address[12]~142 vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|decode_4oa:deep_decode|w_anode231w[2] } "NODE_NAME" } } { "db/decode_4oa.tdf" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/decode_4oa.tdf" 33 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.082 ns) + CELL(0.632 ns) 4.522 ns vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|ram_block1a6~porta_we_reg 4 MEM M4K_X13_Y19 1 " "Info: 4: + IC(2.082 ns) + CELL(0.632 ns) = 4.522 ns; Loc. = M4K_X13_Y19; Fanout = 1; MEM Node = 'vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|ram_block1a6~porta_we_reg'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "2.714 ns" { vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|decode_4oa:deep_decode|w_anode231w[2] vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a6~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_4qc1.tdf" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/altsyncram_4qc1.tdf" 173 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.220 ns ( 26.98 % ) " "Info: Total cell delay = 1.220 ns ( 26.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.302 ns ( 73.02 % ) " "Info: Total interconnect delay = 3.302 ns ( 73.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "4.522 ns" { control_wr_rd_for_SRAM:BLOCK4|wr_address[12] vga_controller:BLOCK2|address[12]~142 vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|decode_4oa:deep_decode|w_anode231w[2] vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a6~porta_we_reg } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "4.522 ns" { control_wr_rd_for_SRAM:BLOCK4|wr_address[12] vga_controller:BLOCK2|address[12]~142 vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|decode_4oa:deep_decode|w_anode231w[2] vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a6~porta_we_reg } { 0.000ns 0.774ns 0.446ns 2.082ns } { 0.000ns 0.438ns 0.150ns 0.632ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.086 ns - Smallest " "Info: - Smallest clock skew is 0.086 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 4.380 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination memory is 4.380 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.331 ns) + CELL(0.787 ns) 2.117 ns clock 2 REG LCFF_X1_Y18_N23 3 " "Info: 2: + IC(0.331 ns) + CELL(0.787 ns) = 2.117 ns; Loc. = LCFF_X1_Y18_N23; Fanout = 3; REG Node = 'clock'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "1.118 ns" { CLOCK_50 clock } "NODE_NAME" } } { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.634 ns) + CELL(0.000 ns) 2.751 ns clock~clkctrl 3 COMB CLKCTRL_G1 1185 " "Info: 3: + IC(0.634 ns) + CELL(0.000 ns) = 2.751 ns; Loc. = CLKCTRL_G1; Fanout = 1185; COMB Node = 'clock~clkctrl'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "0.634 ns" { clock clock~clkctrl } "NODE_NAME" } } { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.968 ns) + CELL(0.661 ns) 4.380 ns vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|ram_block1a6~porta_we_reg 4 MEM M4K_X13_Y19 1 " "Info: 4: + IC(0.968 ns) + CELL(0.661 ns) = 4.380 ns; Loc. = M4K_X13_Y19; Fanout = 1; MEM Node = 'vga_controller:BLOCK2\|ram_vga:VGA_khoi1\|altsyncram:altsyncram_component\|altsyncram_4qc1:auto_generated\|ram_block1a6~porta_we_reg'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "1.629 ns" { clock~clkctrl vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a6~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_4qc1.tdf" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/altsyncram_4qc1.tdf" 173 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.447 ns ( 55.87 % ) " "Info: Total cell delay = 2.447 ns ( 55.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.933 ns ( 44.13 % ) " "Info: Total interconnect delay = 1.933 ns ( 44.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "4.380 ns" { CLOCK_50 clock clock~clkctrl vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a6~porta_we_reg } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "4.380 ns" { CLOCK_50 CLOCK_50~combout clock clock~clkctrl vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a6~porta_we_reg } { 0.000ns 0.000ns 0.331ns 0.634ns 0.968ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.661ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 4.294 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 4.294 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.331 ns) + CELL(0.787 ns) 2.117 ns clock 2 REG LCFF_X1_Y18_N23 3 " "Info: 2: + IC(0.331 ns) + CELL(0.787 ns) = 2.117 ns; Loc. = LCFF_X1_Y18_N23; Fanout = 3; REG Node = 'clock'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "1.118 ns" { CLOCK_50 clock } "NODE_NAME" } } { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.634 ns) + CELL(0.000 ns) 2.751 ns clock~clkctrl 3 COMB CLKCTRL_G1 1185 " "Info: 3: + IC(0.634 ns) + CELL(0.000 ns) = 2.751 ns; Loc. = CLKCTRL_G1; Fanout = 1185; COMB Node = 'clock~clkctrl'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "0.634 ns" { clock clock~clkctrl } "NODE_NAME" } } { "kit_DE2.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.006 ns) + CELL(0.537 ns) 4.294 ns control_wr_rd_for_SRAM:BLOCK4\|wr_address\[12\] 4 REG LCFF_X28_Y10_N21 6 " "Info: 4: + IC(1.006 ns) + CELL(0.537 ns) = 4.294 ns; Loc. = LCFF_X28_Y10_N21; Fanout = 6; REG Node = 'control_wr_rd_for_SRAM:BLOCK4\|wr_address\[12\]'" {  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "1.543 ns" { clock~clkctrl control_wr_rd_for_SRAM:BLOCK4|wr_address[12] } "NODE_NAME" } } { "control_wr_rd_for_SRAM.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/control_wr_rd_for_SRAM.v" 204 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 54.10 % ) " "Info: Total cell delay = 2.323 ns ( 54.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.971 ns ( 45.90 % ) " "Info: Total interconnect delay = 1.971 ns ( 45.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "4.294 ns" { CLOCK_50 clock clock~clkctrl control_wr_rd_for_SRAM:BLOCK4|wr_address[12] } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "4.294 ns" { CLOCK_50 CLOCK_50~combout clock clock~clkctrl control_wr_rd_for_SRAM:BLOCK4|wr_address[12] } { 0.000ns 0.000ns 0.331ns 0.634ns 1.006ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "4.380 ns" { CLOCK_50 clock clock~clkctrl vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a6~porta_we_reg } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "4.380 ns" { CLOCK_50 CLOCK_50~combout clock clock~clkctrl vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a6~porta_we_reg } { 0.000ns 0.000ns 0.331ns 0.634ns 0.968ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.661ns } } } { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "4.294 ns" { CLOCK_50 clock clock~clkctrl control_wr_rd_for_SRAM:BLOCK4|wr_address[12] } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "4.294 ns" { CLOCK_50 CLOCK_50~combout clock clock~clkctrl control_wr_rd_for_SRAM:BLOCK4|wr_address[12] } { 0.000ns 0.000ns 0.331ns 0.634ns 1.006ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "control_wr_rd_for_SRAM.v" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/control_wr_rd_for_SRAM.v" 204 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.035 ns + " "Info: + Micro setup delay of destination is 0.035 ns" {  } { { "db/altsyncram_4qc1.tdf" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/altsyncram_4qc1.tdf" 173 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "4.522 ns" { control_wr_rd_for_SRAM:BLOCK4|wr_address[12] vga_controller:BLOCK2|address[12]~142 vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|decode_4oa:deep_decode|w_anode231w[2] vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a6~porta_we_reg } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "4.522 ns" { control_wr_rd_for_SRAM:BLOCK4|wr_address[12] vga_controller:BLOCK2|address[12]~142 vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|decode_4oa:deep_decode|w_anode231w[2] vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a6~porta_we_reg } { 0.000ns 0.774ns 0.446ns 2.082ns } { 0.000ns 0.438ns 0.150ns 0.632ns } } } { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "4.380 ns" { CLOCK_50 clock clock~clkctrl vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a6~porta_we_reg } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "4.380 ns" { CLOCK_50 CLOCK_50~combout clock clock~clkctrl vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a6~porta_we_reg } { 0.000ns 0.000ns 0.331ns 0.634ns 0.968ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.661ns } } } { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "4.294 ns" { CLOCK_50 clock clock~clkctrl control_wr_rd_for_SRAM:BLOCK4|wr_address[12] } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "4.294 ns" { CLOCK_50 CLOCK_50~combout clock clock~clkctrl control_wr_rd_for_SRAM:BLOCK4|wr_address[12] } { 0.000ns 0.000ns 0.331ns 0.634ns 1.006ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/chuong_trinh/quartusii/win/TimingClosureFloorplan.fld" "" "" { vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a6~porta_we_reg } "NODE_NAME" } } { "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/chuong_trinh/quartusii/win/Technology_Viewer.qrui" "" { vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ram_block1a6~porta_we_reg } {  } {  } } } { "db/altsyncram_4qc1.tdf" "" { Text "C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/altsyncram_4qc1.tdf" 173 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}