kit_de2.hif

VGA sourcecodes/documents

Version 6.0 Build 178 04/27/2006 SJ Web Edition
11
767
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
vga_controller
# storage
db|kit_DE2.(2).cnf
db|kit_DE2.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
vga_controller.v
18ab2573e88bacf7747b0415c274f1c
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
vga_controller:BLOCK2
}
# end
# entity
ram_vga
# storage
db|kit_DE2.(3).cnf
db|kit_DE2.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ram_vga.v
eab331f8d369d9adacb832ddcf6a1
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
vga_controller:BLOCK2|ram_vga:VGA_khoi1
}
# end
# entity
altsyncram_4qc1
# storage
db|kit_DE2.(5).cnf
db|kit_DE2.(5).cnf
# case_insensitive
# source_file
db|altsyncram_4qc1.tdf
f56cbda65db91791c42c922a8d1ba3b
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a13
-1
3
address_a12
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
copy_lena_3.hex
3648f92ab2f3f475c14aafd478a6d1db
}
# hierarchies {
vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated
}
# end
# entity
decode_4oa
# storage
db|kit_DE2.(6).cnf
db|kit_DE2.(6).cnf
# case_insensitive
# source_file
db|decode_4oa.tdf
ffcec87f39aab97a613666ac01fd247
6
# used_port {
eq3
-1
3
eq2
-1
3
eq1
-1
3
eq0
-1
3
enable
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|decode_4oa:decode3
}
# end
# entity
decode_4oa
# storage
db|kit_DE2.(7).cnf
db|kit_DE2.(7).cnf
# case_insensitive
# source_file
db|decode_4oa.tdf
ffcec87f39aab97a613666ac01fd247
6
# used_port {
eq3
-1
3
eq2
-1
3
eq1
-1
3
eq0
-1
3
data1
-1
3
data0
-1
3
enable
-1
2
}
# hierarchies {
vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|decode_4oa:deep_decode
}
# end
# entity
mux_kib
# storage
db|kit_DE2.(8).cnf
db|kit_DE2.(8).cnf
# case_insensitive
# source_file
db|mux_kib.tdf
8fd4e79ecd2a6d7afc30ef526d1440b9
6
# used_port {
sel1
-1
3
sel0
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data31
-1
3
data30
-1
3
data3
-1
3
data29
-1
3
data28
-1
3
data27
-1
3
data26
-1
3
data25
-1
3
data24
-1
3
data23
-1
3
data22
-1
3
data21
-1
3
data20
-1
3
data2
-1
3
data19
-1
3
data18
-1
3
data17
-1
3
data16
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|mux_kib:mux2
}
# end
# entity
vga_sync
# storage
db|kit_DE2.(9).cnf
db|kit_DE2.(9).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
vga_sync.v
f9ebaaff2335fd68d39f5bac8e59b17
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
vga_controller:BLOCK2|vga_sync:VGA_khoi2
}
# end
# entity
D_FFs
# storage
db|kit_DE2.(10).cnf
db|kit_DE2.(10).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
vga_sync.v
f9ebaaff2335fd68d39f5bac8e59b17
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
vga_controller:BLOCK2|vga_sync:VGA_khoi2|D_FFs:V1
vga_controller:BLOCK2|vga_sync:VGA_khoi2|D_FFs:V2
vga_controller:BLOCK2|vga_sync:VGA_khoi2|D_FFs:V3
vga_controller:BLOCK2|vga_sync:VGA_khoi2|D_FFs:A1
vga_controller:BLOCK2|vga_sync:VGA_khoi2|D_FFs:A2
vga_controller:BLOCK2|vga_sync:VGA_khoi2|D_FFs:B3
vga_controller:BLOCK2|vga_sync:VGA_khoi2|D_FFs:B4
vga_controller:BLOCK2|D_FFs:C2
vga_controller:BLOCK2|D_FFs:C3
vga_controller:BLOCK2|D_FFs:C4
vga_controller:BLOCK2|D_FFs:C5
vga_controller:BLOCK2|D_FFs:C6
vga_controller:BLOCK2|D_FFs:C7
vga_controller:BLOCK2|D_FFs:C8
vga_controller:BLOCK2|D_FFs:C9
vga_controller:BLOCK2|Khoi_phat_hien_canh_len:VGA_CONTROLLER|D_FFs:C10
vga_controller:BLOCK2|Khoi_phat_hien_canh_len:VGA_CONTROLLER|D_FFs:C11
vga_controller:BLOCK2|D_FFs:C12
control_wr_rd_for_SRAM:BLOCK4|D_FFs:C13
control_wr_rd_for_SRAM:BLOCK4|D_FFs:C14
control_wr_rd_for_SRAM:BLOCK4|D_FFs:C15
control_wr_rd_for_SRAM:BLOCK4|Khoi_phat_hien_canh_len:BLOCK_DE|D_FFs:C10
control_wr_rd_for_SRAM:BLOCK4|Khoi_phat_hien_canh_len:BLOCK_DE|D_FFs:C11
Khoi_phat_hien_canh_len:BLOCK_DE2|D_FFs:C10
Khoi_phat_hien_canh_len:BLOCK_DE2|D_FFs:C11
Khoi_FIFO:BLOCK_5|Khoi_phat_hien_canh_len:comb_76|D_FFs:C10
Khoi_FIFO:BLOCK_5|Khoi_phat_hien_canh_len:comb_76|D_FFs:C11
}
# end
# entity
Khoi_phat_hien_canh_len
# storage
db|kit_DE2.(11).cnf
db|kit_DE2.(11).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
vga_controller.v
18ab2573e88bacf7747b0415c274f1c
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
vga_controller:BLOCK2|Khoi_phat_hien_canh_len:VGA_CONTROLLER
control_wr_rd_for_SRAM:BLOCK4|Khoi_phat_hien_canh_len:BLOCK_DE
Khoi_phat_hien_canh_len:BLOCK_DE2
Khoi_FIFO:BLOCK_5|Khoi_phat_hien_canh_len:comb_76
}
# end
# entity
SRAM_interface
# storage
db|kit_DE2.(12).cnf
db|kit_DE2.(12).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SRAM_interface.v
24bb9dfb6a857a041bfcf5abba604f
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SRAM_interface:BLOCK3
}
# end
# entity
FIFO_Image
# storage
db|kit_DE2.(15).cnf
db|kit_DE2.(15).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
FIFO_Image.v
9922bc922f234d963db7f073179b7
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_0
Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_1
}
# end
# entity
scfifo_1eu
# storage
db|kit_DE2.(17).cnf
db|kit_DE2.(17).cnf
# case_insensitive
# source_file
db|scfifo_1eu.tdf
da5b4d61b5ce60904c3c28b1a19d2
6
# used_port {
wrreq
-1
3
rdreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
}
# hierarchies {
Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_0|scfifo:scfifo_component|scfifo_1eu:auto_generated
Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_1|scfifo:scfifo_component|scfifo_1eu:auto_generated
}
# end
# entity
a_dpfifo_8ku
# storage
db|kit_DE2.(18).cnf
db|kit_DE2.(18).cnf
# case_insensitive
# source_file
db|a_dpfifo_8ku.tdf
39d31aa6b26a88d7ed61811f9a7ef41a
6
# used_port {
wreq
-1
3
sclr
-1
3
rreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
}
# hierarchies {
Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_0|scfifo:scfifo_component|scfifo_1eu:auto_generated|a_dpfifo_8ku:dpfifo
Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_1|scfifo:scfifo_component|scfifo_1eu:auto_generated|a_dpfifo_8ku:dpfifo
}
# end
# entity
a_fefifo_u7e
# storage
db|kit_DE2.(19).cnf
db|kit_DE2.(19).cnf
# case_insensitive
# source_file
db|a_fefifo_u7e.tdf
693322f883c2fb7e1585c05fd54653
6
# used_port {
wreq
-1
3
sclr
-1
3
rreq
-1
3
full
-1
3
empty
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_0|scfifo:scfifo_component|scfifo_1eu:auto_generated|a_dpfifo_8ku:dpfifo|a_fefifo_u7e:fifo_state
Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_1|scfifo:scfifo_component|scfifo_1eu:auto_generated|a_dpfifo_8ku:dpfifo|a_fefifo_u7e:fifo_state
}
# end
# entity
cntr_sj7
# storage
db|kit_DE2.(20).cnf
db|kit_DE2.(20).cnf
# case_insensitive
# source_file
db|cntr_sj7.tdf
71c6911a667c10b2df7548593155835
6
# used_port {
updown
-1
3
sclr
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_0|scfifo:scfifo_component|scfifo_1eu:auto_generated|a_dpfifo_8ku:dpfifo|a_fefifo_u7e:fifo_state|cntr_sj7:count_usedw
Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_1|scfifo:scfifo_component|scfifo_1eu:auto_generated|a_dpfifo_8ku:dpfifo|a_fefifo_u7e:fifo_state|cntr_sj7:count_usedw
}
# end
# entity
dpram_4it
# storage
db|kit_DE2.(21).cnf
db|kit_DE2.(21).cnf
# case_insensitive
# source_file
db|dpram_4it.tdf
a1c2f33c6a2776c6d8de23a33346cd7
6
# used_port {
wren
-1
3
wraddress6
-1
3
wraddress5
-1
3
wraddress4
-1
3
wraddress3
-1
3
wraddress2
-1
3
wraddress1
-1
3
wraddress0
-1
3
rdaddress6
-1
3
rdaddress5
-1
3
rdaddress4
-1
3
rdaddress3
-1
3
rdaddress2
-1
3
rdaddress1