kit_de2.hier_info

VGA sourcecodes/documents

register3[5] <= register3[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register3[6] <= register3[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register3[7] <= register3[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register4[0] <= register4[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register4[1] <= register4[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register4[2] <= register4[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register4[3] <= register4[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register4[4] <= register4[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register4[5] <= register4[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register4[6] <= register4[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register4[7] <= register4[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register5[0] <= register5[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register5[1] <= register5[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register5[2] <= register5[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register5[3] <= register5[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register5[4] <= register5[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register5[5] <= register5[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register5[6] <= register5[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register5[7] <= register5[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register6[0] <= register6[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register6[1] <= register6[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register6[2] <= register6[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register6[3] <= register6[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register6[4] <= register6[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register6[5] <= register6[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register6[6] <= register6[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register6[7] <= register6[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register7[0] <= register7[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register7[1] <= register7[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register7[2] <= register7[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register7[3] <= register7[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register7[4] <= register7[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register7[5] <= register7[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register7[6] <= register7[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register7[7] <= register7[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register8[0] <= register8[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register8[1] <= register8[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register8[2] <= register8[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register8[3] <= register8[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register8[4] <= register8[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register8[5] <= register8[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register8[6] <= register8[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register8[7] <= register8[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register9[0] <= register9[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register9[1] <= register9[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register9[2] <= register9[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register9[3] <= register9[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register9[4] <= register9[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register9[5] <= register9[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register9[6] <= register9[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register9[7] <= register9[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|Khoi_FIFO:BLOCK_5|Khoi_phat_hien_canh_len:comb_76
clock => clock~0.IN2
in => in~0.IN1
out <= out~0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|Khoi_FIFO:BLOCK_5|Khoi_phat_hien_canh_len:comb_76|D_FFs:C10
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|Khoi_FIFO:BLOCK_5|Khoi_phat_hien_canh_len:comb_76|D_FFs:C11
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_0
clock => clock~0.IN1
data[0] => data[0]~7.IN1
data[1] => data[1]~6.IN1
data[2] => data[2]~5.IN1
data[3] => data[3]~4.IN1
data[4] => data[4]~3.IN1
data[5] => data[5]~2.IN1
data[6] => data[6]~1.IN1
data[7] => data[7]~0.IN1
rdreq => rdreq~0.IN1
wrreq => wrreq~0.IN1
q[0] <= scfifo:scfifo_component.q
q[1] <= scfifo:scfifo_component.q
q[2] <= scfifo:scfifo_component.q
q[3] <= scfifo:scfifo_component.q
q[4] <= scfifo:scfifo_component.q
q[5] <= scfifo:scfifo_component.q
q[6] <= scfifo:scfifo_component.q
q[7] <= scfifo:scfifo_component.q


|kit_DE2|Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_0|scfifo:scfifo_component
data[0] => scfifo_1eu:auto_generated.data[0]
data[1] => scfifo_1eu:auto_generated.data[1]
data[2] => scfifo_1eu:auto_generated.data[2]
data[3] => scfifo_1eu:auto_generated.data[3]
data[4] => scfifo_1eu:auto_generated.data[4]
data[5] => scfifo_1eu:auto_generated.data[5]
data[6] => scfifo_1eu:auto_generated.data[6]
data[7] => scfifo_1eu:auto_generated.data[7]
q[0] <= scfifo_1eu:auto_generated.q[0]
q[1] <= scfifo_1eu:auto_generated.q[1]
q[2] <= scfifo_1eu:auto_generated.q[2]
q[3] <= scfifo_1eu:auto_generated.q[3]
q[4] <= scfifo_1eu:auto_generated.q[4]
q[5] <= scfifo_1eu:auto_generated.q[5]
q[6] <= scfifo_1eu:auto_generated.q[6]
q[7] <= scfifo_1eu:auto_generated.q[7]
wrreq => scfifo_1eu:auto_generated.wrreq
rdreq => scfifo_1eu:auto_generated.rdreq
clock => scfifo_1eu:auto_generated.clock
aclr => ~NO_FANOUT~
sclr => ~NO_FANOUT~
empty <= <GND>
full <= <GND>
almost_full <= <GND>
almost_empty <= <GND>
usedw[0] <= <GND>
usedw[1] <= <GND>
usedw[2] <= <GND>
usedw[3] <= <GND>
usedw[4] <= <GND>
usedw[5] <= <GND>
usedw[6] <= <GND>


|kit_DE2|Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_0|scfifo:scfifo_component|scfifo_1eu:auto_generated
clock => a_dpfifo_8ku:dpfifo.clock
data[0] => a_dpfifo_8ku:dpfifo.data[0]
data[1] => a_dpfifo_8ku:dpfifo.data[1]
data[2] => a_dpfifo_8ku:dpfifo.data[2]
data[3] => a_dpfifo_8ku:dpfifo.data[3]
data[4] => a_dpfifo_8ku:dpfifo.data[4]
data[5] => a_dpfifo_8ku:dpfifo.data[5]
data[6] => a_dpfifo_8ku:dpfifo.data[6]
data[7] => a_dpfifo_8ku:dpfifo.data[7]
q[0] <= a_dpfifo_8ku:dpfifo.q[0]
q[1] <= a_dpfifo_8ku:dpfifo.q[1]
q[2] <= a_dpfifo_8ku:dpfifo.q[2]
q[3] <= a_dpfifo_8ku:dpfifo.q[3]
q[4] <= a_dpfifo_8ku:dpfifo.q[4]
q[5] <= a_dpfifo_8ku:dpfifo.q[5]
q[6] <= a_dpfifo_8ku:dpfifo.q[6]
q[7] <= a_dpfifo_8ku:dpfifo.q[7]
rdreq => a_dpfifo_8ku:dpfifo.rreq
wrreq => a_dpfifo_8ku:dpfifo.wreq


|kit_DE2|Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_0|scfifo:scfifo_component|scfifo_1eu:auto_generated|a_dpfifo_8ku:dpfifo
clock => a_fefifo_u7e:fifo_state.clock
clock => dpram_4it:FIFOram.inclock
clock => dpram_4it:FIFOram.outclock
clock => cntr_el8:rd_ptr_count.clock
clock => cntr_el8:wr_ptr.clock
data[0] => dpram_4it:FIFOram.data[0]
data[1] => dpram_4it:FIFOram.data[1]
data[2] => dpram_4it:FIFOram.data[2]
data[3] => dpram_4it:FIFOram.data[3]
data[4] => dpram_4it:FIFOram.data[4]
data[5] => dpram_4it:FIFOram.data[5]
data[6] => dpram_4it:FIFOram.data[6]
data[7] => dpram_4it:FIFOram.data[7]
q[0] <= dpram_4it:FIFOram.q[0]
q[1] <= dpram_4it:FIFOram.q[1]
q[2] <= dpram_4it:FIFOram.q[2]
q[3] <= dpram_4it:FIFOram.q[3]
q[4] <= dpram_4it:FIFOram.q[4]
q[5] <= dpram_4it:FIFOram.q[5]
q[6] <= dpram_4it:FIFOram.q[6]
q[7] <= dpram_4it:FIFOram.q[7]
rreq => a_fefifo_u7e:fifo_state.rreq
rreq => valid_rreq.IN0
sclr => a_fefifo_u7e:fifo_state.sclr
sclr => cntr_el8:rd_ptr_count.sclr
sclr => cntr_el8:wr_ptr.sclr
wreq => a_fefifo_u7e:fifo_state.wreq
wreq => valid_wreq.IN0


|kit_DE2|Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_0|scfifo:scfifo_component|scfifo_1eu:auto_generated|a_dpfifo_8ku:dpfifo|a_fefifo_u7e:fifo_state
aclr => cntr_sj7:count_usedw.aclr
clock => cntr_sj7:count_usedw.clock
clock => b_full.CLK
clock => b_non_empty.CLK
full <= b_full.DB_MAX_OUTPUT_PORT_TYPE
rreq => valid_rreq.IN0
sclr => cntr_sj7:count_usedw.sclr
wreq => valid_wreq.IN0


|kit_DE2|Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_0|scfifo:scfifo_component|scfifo_1eu:auto_generated|a_dpfifo_8ku:dpfifo|a_fefifo_u7e:fifo_state|cntr_sj7:count_usedw
aclr => counter_reg_bit1a[6].ACLR
aclr => counter_reg_bit1a[5].ACLR
aclr => counter_reg_bit1a[4].ACLR
aclr => counter_reg_bit1a[3].ACLR
aclr => counter_reg_bit1a[2].ACLR
aclr => counter_reg_bit1a[1].ACLR
aclr => counter_reg_bit1a[0].ACLR
clock => counter_reg_bit1a[6].CLK
clock => counter_reg_bit1a[5].CLK
clock => counter_reg_bit1a[4].CLK
clock => counter_reg_bit1a[3].CLK
clock => counter_reg_bit1a[2].CLK
clock => counter_reg_bit1a[1].CLK
clock => counter_reg_bit1a[0].CLK
q[0] <= counter_reg_bit1a[0].REGOUT
q[1] <= counter_reg_bit1a[1].REGOUT
q[2] <= counter_reg_bit1a[2].REGOUT
q[3] <= counter_reg_bit1a[3].REGOUT
q[4] <= counter_reg_bit1a[4].REGOUT
q[5] <= counter_reg_bit1a[5].REGOUT
q[6] <= counter_reg_bit1a[6].REGOUT
updown => counter_comb_bita0.DATAB
updown => counter_comb_bita1.DATAB
updown => counter_comb_bita2.DATAB
updown => counter_comb_bita3.DATAB
updown => counter_comb_bita4.DATAB
updown => counter_comb_bita5.DATAB
updown => counter_comb_bita6.DATAB


|kit_DE2|Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_0|scfifo:scfifo_component|scfifo_1eu:auto_generated|a_dpfifo_8ku:dpfifo|dpram_4it:FIFOram
data[0] => altsyncram_6sj1:altsyncram2.data_a[0]
data[1] => altsyncram_6sj1:altsyncram2.data_a[1]
data[2] => altsyncram_6sj1:altsyncram2.data_a[2]
data[3] => altsyncram_6sj1:altsyncram2.data_a[3]
data[4] => altsyncram_6sj1:altsyncram2.data_a[4]
data[5] => altsyncram_6sj1:altsyncram2.data_a[5]
data[6] => altsyncram_6sj1:altsyncram2.data_a[6]
data[7] => altsyncram_6sj1:altsyncram2.data_a[7]
inclock => altsyncram_6sj1:altsyncram2.clock0
outclock => altsyncram_6sj1:altsyncram2.clock1
outclocken => altsyncram_6sj1:altsyncram2.clocken1
q[0] <= altsyncram_6sj1:altsyncram2.q_b[0]
q[1] <= altsyncram_6sj1:altsyncram2.q_b[1]
q[2] <= altsyncram_6sj1:altsyncram2.q_b[2]
q[3] <= altsyncram_6sj1:altsyncram2.q_b[3]
q[4] <= altsyncram_6sj1:altsyncram2.q_b[4]
q[5] <= altsyncram_6sj1:altsyncram2.q_b[5]
q[6] <= altsyncram_6sj1:altsyncram2.q_b[6]
q[7] <= altsyncram_6sj1:altsyncram2.q_b[7]
rdaddress[0] => altsyncram_6sj1:altsyncram2.address_b[0]
rdaddress[1] => altsyncram_6sj1:altsyncram2.address_b[1]
rdaddress[2] => altsyncram_6sj1:altsyncram2.address_b[2]
rdaddress[3] => altsyncram_6sj1:altsyncram2.address_b[3]
rdaddress[4] => altsyncram_6sj1:altsyncram2.address_b[4]
rdaddress[5] => altsyncram_6sj1:altsyncram2.address_b[5]
rdaddress[6] => altsyncram_6sj1:altsyncram2.address_b[6]
wraddress[0] => altsyncram_6sj1:altsyncram2.address_a[0]
wraddress[1] => altsyncram_6sj1:altsyncram2.address_a[1]
wraddress[2] => altsyncram_6sj1:altsyncram2.address_a[2]
wraddress[3] => altsyncram_6sj1:altsyncram2.address_a[3]
wraddress[4] => altsyncram_6sj1:altsyncram2.address_a[4]
wraddress[5] => altsyncram_6sj1:altsyncram2.address_a[5]
wraddress[6] => altsyncram_6sj1:altsyncram2.address_a[6]
wren => altsyncram_6sj1:altsyncram2.wren_a


|kit_DE2|Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_0|scfifo:scfifo_component|scfifo_1eu:auto_generated|a_dpfifo_8ku:dpfifo|dpram_4it:FIFOram|altsyncram_6sj1:altsyncram2
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4
address_a[4] => ram_block3a7.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[5] => ram_block3a4.PORTAADDR5
address_a[5] => ram_block3a5.PORTAADDR5
address_a[5] => ram_block3a6.PORTAADDR5
address_a[5] => ram_block3a7.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[6] => ram_block3a4.PORTAADDR6
address_a[6] => ram_block3a5.PORTAADDR6
address_a[6] => ram_block3a6.PORTAADDR6
address_a[6] => ram_block3a7.PORTAADDR6
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[0] => ram_block3a4.PORTBADDR
address_b[0] => ram_block3a5.PORTBADDR
address_b[0] => ram_block3a6.