kit_de2.hier_info

VGA sourcecodes/documents

in_address[8] => oSRAM_ADDR[8].DATAIN
in_address[9] => oSRAM_ADDR[9].DATAIN
in_address[10] => oSRAM_ADDR[10].DATAIN
in_address[11] => oSRAM_ADDR[11].DATAIN
in_address[12] => oSRAM_ADDR[12].DATAIN
in_address[13] => oSRAM_ADDR[13].DATAIN
in_address[14] => oSRAM_ADDR[14].DATAIN
in_address[15] => oSRAM_ADDR[15].DATAIN
in_address[16] => oSRAM_ADDR[16].DATAIN
in_address[17] => oSRAM_ADDR[17].DATAIN
wr_or_rd => oSRAM_DQ~16.OE
wr_or_rd => oSRAM_DQ~17.OE
wr_or_rd => oSRAM_DQ~18.OE
wr_or_rd => oSRAM_DQ~19.OE
wr_or_rd => oSRAM_DQ~20.OE
wr_or_rd => oSRAM_DQ~21.OE
wr_or_rd => oSRAM_DQ~22.OE
wr_or_rd => oSRAM_DQ~23.OE
wr_or_rd => oSRAM_DQ~24.OE
wr_or_rd => oSRAM_DQ~25.OE
wr_or_rd => oSRAM_DQ~26.OE
wr_or_rd => oSRAM_DQ~27.OE
wr_or_rd => oSRAM_DQ~28.OE
wr_or_rd => oSRAM_DQ~29.OE
wr_or_rd => oSRAM_DQ~30.OE
wr_or_rd => oSRAM_DQ~31.OE
wr_or_rd => oSRAM_WE_N.DATAIN
wr_or_rd => oSRAM_OE_N.DATAIN
in_data[0] => oSRAM_DQ~31.DATAIN
in_data[1] => oSRAM_DQ~30.DATAIN
in_data[2] => oSRAM_DQ~29.DATAIN
in_data[3] => oSRAM_DQ~28.DATAIN
in_data[4] => oSRAM_DQ~27.DATAIN
in_data[5] => oSRAM_DQ~26.DATAIN
in_data[6] => oSRAM_DQ~25.DATAIN
in_data[7] => oSRAM_DQ~24.DATAIN
in_data[8] => oSRAM_DQ~23.DATAIN
in_data[9] => oSRAM_DQ~22.DATAIN
in_data[10] => oSRAM_DQ~21.DATAIN
in_data[11] => oSRAM_DQ~20.DATAIN
in_data[12] => oSRAM_DQ~19.DATAIN
in_data[13] => oSRAM_DQ~18.DATAIN
in_data[14] => oSRAM_DQ~17.DATAIN
in_data[15] => oSRAM_DQ~16.DATAIN
oSRAM_DQ[0] <= oSRAM_DQ~31
oSRAM_DQ[1] <= oSRAM_DQ~30
oSRAM_DQ[2] <= oSRAM_DQ~29
oSRAM_DQ[3] <= oSRAM_DQ~28
oSRAM_DQ[4] <= oSRAM_DQ~27
oSRAM_DQ[5] <= oSRAM_DQ~26
oSRAM_DQ[6] <= oSRAM_DQ~25
oSRAM_DQ[7] <= oSRAM_DQ~24
oSRAM_DQ[8] <= oSRAM_DQ~23
oSRAM_DQ[9] <= oSRAM_DQ~22
oSRAM_DQ[10] <= oSRAM_DQ~21
oSRAM_DQ[11] <= oSRAM_DQ~20
oSRAM_DQ[12] <= oSRAM_DQ~19
oSRAM_DQ[13] <= oSRAM_DQ~18
oSRAM_DQ[14] <= oSRAM_DQ~17
oSRAM_DQ[15] <= oSRAM_DQ~16
oSRAM_ADDR[0] <= in_address[0].DB_MAX_OUTPUT_PORT_TYPE
oSRAM_ADDR[1] <= in_address[1].DB_MAX_OUTPUT_PORT_TYPE
oSRAM_ADDR[2] <= in_address[2].DB_MAX_OUTPUT_PORT_TYPE
oSRAM_ADDR[3] <= in_address[3].DB_MAX_OUTPUT_PORT_TYPE
oSRAM_ADDR[4] <= in_address[4].DB_MAX_OUTPUT_PORT_TYPE
oSRAM_ADDR[5] <= in_address[5].DB_MAX_OUTPUT_PORT_TYPE
oSRAM_ADDR[6] <= in_address[6].DB_MAX_OUTPUT_PORT_TYPE
oSRAM_ADDR[7] <= in_address[7].DB_MAX_OUTPUT_PORT_TYPE
oSRAM_ADDR[8] <= in_address[8].DB_MAX_OUTPUT_PORT_TYPE
oSRAM_ADDR[9] <= in_address[9].DB_MAX_OUTPUT_PORT_TYPE
oSRAM_ADDR[10] <= in_address[10].DB_MAX_OUTPUT_PORT_TYPE
oSRAM_ADDR[11] <= in_address[11].DB_MAX_OUTPUT_PORT_TYPE
oSRAM_ADDR[12] <= in_address[12].DB_MAX_OUTPUT_PORT_TYPE
oSRAM_ADDR[13] <= in_address[13].DB_MAX_OUTPUT_PORT_TYPE
oSRAM_ADDR[14] <= in_address[14].DB_MAX_OUTPUT_PORT_TYPE
oSRAM_ADDR[15] <= in_address[15].DB_MAX_OUTPUT_PORT_TYPE
oSRAM_ADDR[16] <= in_address[16].DB_MAX_OUTPUT_PORT_TYPE
oSRAM_ADDR[17] <= in_address[17].DB_MAX_OUTPUT_PORT_TYPE
oSRAM_UB_N <= <GND>
oSRAM_LB_N <= <GND>
oSRAM_WE_N <= wr_or_rd.DB_MAX_OUTPUT_PORT_TYPE
oSRAM_CE_N <= <GND>
oSRAM_OE_N <= wr_or_rd.DB_MAX_OUTPUT_PORT_TYPE
data_ram_vga[0] <= data_ram_vga~15.DB_MAX_OUTPUT_PORT_TYPE
data_ram_vga[1] <= data_ram_vga~14.DB_MAX_OUTPUT_PORT_TYPE
data_ram_vga[2] <= data_ram_vga~13.DB_MAX_OUTPUT_PORT_TYPE
data_ram_vga[3] <= data_ram_vga~12.DB_MAX_OUTPUT_PORT_TYPE
data_ram_vga[4] <= data_ram_vga~11.DB_MAX_OUTPUT_PORT_TYPE
data_ram_vga[5] <= data_ram_vga~10.DB_MAX_OUTPUT_PORT_TYPE
data_ram_vga[6] <= data_ram_vga~9.DB_MAX_OUTPUT_PORT_TYPE
data_ram_vga[7] <= data_ram_vga~8.DB_MAX_OUTPUT_PORT_TYPE
data_ram_vga[8] <= data_ram_vga~7.DB_MAX_OUTPUT_PORT_TYPE
data_ram_vga[9] <= data_ram_vga~6.DB_MAX_OUTPUT_PORT_TYPE
data_ram_vga[10] <= data_ram_vga~5.DB_MAX_OUTPUT_PORT_TYPE
data_ram_vga[11] <= data_ram_vga~4.DB_MAX_OUTPUT_PORT_TYPE
data_ram_vga[12] <= data_ram_vga~3.DB_MAX_OUTPUT_PORT_TYPE
data_ram_vga[13] <= data_ram_vga~2.DB_MAX_OUTPUT_PORT_TYPE
data_ram_vga[14] <= data_ram_vga~1.DB_MAX_OUTPUT_PORT_TYPE
data_ram_vga[15] <= data_ram_vga~0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|control_wr_rd_for_SRAM:BLOCK4
clock => clock~0.IN4
reset => reset~0.IN3
key => key~0.IN1
sw => hanh.OUTPUTSELECT
signal_data_valid => next_state~2.DATAB
signal_data_valid => next_state~0.DATAB
signal_data_valid => always2~0.IN1
signal_data_valid => always2~1.IN1
signal_data_valid => Selector0.IN2
signal_data_valid => Selector1.IN2
data_value[0] => data_low[0].DATAIN
data_value[0] => data_high[0].DATAIN
data_value[1] => data_low[1].DATAIN
data_value[1] => data_high[1].DATAIN
data_value[2] => data_low[2].DATAIN
data_value[2] => data_high[2].DATAIN
data_value[3] => data_low[3].DATAIN
data_value[3] => data_high[3].DATAIN
data_value[4] => data_low[4].DATAIN
data_value[4] => data_high[4].DATAIN
data_value[5] => data_low[5].DATAIN
data_value[5] => data_high[5].DATAIN
data_value[6] => data_low[6].DATAIN
data_value[6] => data_high[6].DATAIN
data_value[7] => data_low[7].DATAIN
data_value[7] => data_high[7].DATAIN
wr_request => flag_rd_start_in.IN1
done_dislay1 => set_start_write_image.IN0
in_address[0] <= in_address[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_address[1] <= in_address[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_address[2] <= in_address[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_address[3] <= in_address[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_address[4] <= in_address[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_address[5] <= in_address[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_address[6] <= in_address[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_address[7] <= in_address[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_address[8] <= in_address[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_address[9] <= in_address[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_address[10] <= in_address[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_address[11] <= in_address[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_address[12] <= in_address[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_address[13] <= in_address[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_address[14] <= in_address[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_address[15] <= in_address[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_address[16] <= in_address[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_address[17] <= in_address[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wr_or_rd <= wr_or_rd~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_data[0] <= in_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_data[1] <= in_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_data[2] <= in_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_data[3] <= in_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_data[4] <= in_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_data[5] <= in_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_data[6] <= in_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_data[7] <= in_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_data[8] <= in_data[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_data[9] <= in_data[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_data[10] <= in_data[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_data[11] <= in_data[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_data[12] <= in_data[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_data[13] <= in_data[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_data[14] <= in_data[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
in_data[15] <= in_data[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_Ram_vga[0] => data_colour_in[0].DATAA
data_Ram_vga[1] => data_colour_in[1].DATAA
data_Ram_vga[2] => data_colour_in[2].DATAA
data_Ram_vga[3] => data_colour_in[3].DATAA
data_Ram_vga[4] => data_colour_in[4].DATAA
data_Ram_vga[5] => data_colour_in[5].DATAA
data_Ram_vga[6] => data_colour_in[6].DATAA
data_Ram_vga[7] => data_colour_in[7].DATAA
data_Ram_vga[8] => data_colour_in[0].DATAB
data_Ram_vga[9] => data_colour_in[1].DATAB
data_Ram_vga[10] => data_colour_in[2].DATAB
data_Ram_vga[11] => data_colour_in[3].DATAB
data_Ram_vga[12] => data_colour_in[4].DATAB
data_Ram_vga[13] => data_colour_in[5].DATAB
data_Ram_vga[14] => data_colour_in[6].DATAB
data_Ram_vga[15] => data_colour_in[7].DATAB
wr_address[0] <= wr_address[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wr_address[1] <= wr_address[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wr_address[2] <= wr_address[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wr_address[3] <= wr_address[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wr_address[4] <= wr_address[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wr_address[5] <= wr_address[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wr_address[6] <= wr_address[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wr_address[7] <= wr_address[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wr_address[8] <= wr_address[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wr_address[9] <= wr_address[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wr_address[10] <= wr_address[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wr_address[11] <= wr_address[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wr_address[12] <= wr_address[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wr_address[13] <= wr_address[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
do_write <= D_FFs:C14.port3
data_colour[0] <= data_colour[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_colour[1] <= data_colour[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_colour[2] <= data_colour[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_colour[3] <= data_colour[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_colour[4] <= data_colour[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_colour[5] <= data_colour[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_colour[6] <= data_colour[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_colour[7] <= data_colour[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
clear_do_read_on_SRAM <= D_FFs:C15.port3
enable_do_read_on_SRAM <= enable_do_read_on_SRAM~reg0.DB_MAX_OUTPUT_PORT_TYPE
wr_address_SRAM[0] <= counter_address_wr[0].DB_MAX_OUTPUT_PORT_TYPE
wr_address_SRAM[1] <= counter_address_wr[1].DB_MAX_OUTPUT_PORT_TYPE
wr_address_SRAM[2] <= counter_address_wr[2].DB_MAX_OUTPUT_PORT_TYPE
wr_address_SRAM[3] <= counter_address_wr[3].DB_MAX_OUTPUT_PORT_TYPE
wr_address_SRAM[4] <= counter_address_wr[4].DB_MAX_OUTPUT_PORT_TYPE
wr_address_SRAM[5] <= counter_address_wr[5].DB_MAX_OUTPUT_PORT_TYPE
wr_address_SRAM[6] <= counter_address_wr[6].DB_MAX_OUTPUT_PORT_TYPE
wr_address_SRAM[7] <= counter_address_wr[7].DB_MAX_OUTPUT_PORT_TYPE
wr_address_SRAM[8] <= counter_address_wr[8].DB_MAX_OUTPUT_PORT_TYPE
wr_address_SRAM[9] <= counter_address_wr[9].DB_MAX_OUTPUT_PORT_TYPE
wr_address_SRAM[10] <= counter_address_wr[10].DB_MAX_OUTPUT_PORT_TYPE
wr_address_SRAM[11] <= counter_address_wr[11].DB_MAX_OUTPUT_PORT_TYPE
wr_address_SRAM[12] <= counter_address_wr[12].DB_MAX_OUTPUT_PORT_TYPE
wr_address_SRAM[13] <= counter_address_wr[13].DB_MAX_OUTPUT_PORT_TYPE
wr_address_SRAM[14] <= counter_address_wr[14].DB_MAX_OUTPUT_PORT_TYPE
wr_address_SRAM[15] <= counter_address_wr[15].DB_MAX_OUTPUT_PORT_TYPE
wr_address_SRAM[16] <= counter_address_wr[16].DB_MAX_OUTPUT_PORT_TYPE
wr_address_SRAM[17] <= counter_address_wr[17].DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|control_wr_rd_for_SRAM:BLOCK4|D_FFs:C13
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|control_wr_rd_for_SRAM:BLOCK4|D_FFs:C14
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|control_wr_rd_for_SRAM:BLOCK4|D_FFs:C15
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|control_wr_rd_for_SRAM:BLOCK4|Khoi_phat_hien_canh_len:BLOCK_DE
clock => clock~0.IN2
in => in~0.IN1
out <= out~0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|control_wr_rd_for_SRAM:BLOCK4|Khoi_phat_hien_canh_len:BLOCK_DE|D_FFs:C10
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|control_wr_rd_for_SRAM:BLOCK4|Khoi_phat_hien_canh_len:BLOCK_DE|D_FFs:C11
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|Khoi_phat_hien_canh_len:BLOCK_DE2
clock => clock~0.IN2
in => in~0.IN1
out <= out~0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|Khoi_phat_hien_canh_len:BLOCK_DE2|D_FFs:C10
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|Khoi_phat_hien_canh_len:BLOCK_DE2|D_FFs:C11
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|Khoi_FIFO:BLOCK_5
clock => clock~0.IN3
reset => count_temp[6].ACLR
reset => count_temp[5].ACLR
reset => count_temp[4].ACLR
reset => count_temp[3].ACLR
reset => count_temp[2].ACLR
reset => count_temp[1].ACLR
reset => count_temp[0].ACLR
reset => signal_data_valid~reg0.ACLR
reset => count_temp[7].ACLR
data_from_UART[0] => data_from_UART[0]~7.IN1
data_from_UART[1] => data_from_UART[1]~6.IN1
data_from_UART[2] => data_from_UART[2]~5.IN1
data_from_UART[3] => data_from_UART[3]~4.IN1
data_from_UART[4] => data_from_UART[4]~3.IN1
data_from_UART[5] => data_from_UART[5]~2.IN1
data_from_UART[6] => data_from_UART[6]~1.IN1
data_from_UART[7] => data_from_UART[7]~0.IN1
data_ready_from_UART => data_ready_from_UART~0.IN3
signal_data_valid <= signal_data_valid~reg0.DB_MAX_OUTPUT_PORT_TYPE
register1[0] <= register1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register1[1] <= register1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register1[2] <= register1[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register1[3] <= register1[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register1[4] <= register1[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register1[5] <= register1[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register1[6] <= register1[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register1[7] <= register1[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register2[0] <= register2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register2[1] <= register2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register2[2] <= register2[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register2[3] <= register2[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register2[4] <= register2[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register2[5] <= register2[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register2[6] <= register2[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register2[7] <= register2[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register3[0] <= register3[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register3[1] <= register3[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register3[2] <= register3[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register3[3] <= register3[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
register3[4] <= register3[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE