kit_de2.hier_info

VGA sourcecodes/documents

address_a[11] => ram_block1a0.PORTAADDR11
address_a[11] => ram_block1a1.PORTAADDR11
address_a[11] => ram_block1a2.PORTAADDR11
address_a[11] => ram_block1a3.PORTAADDR11
address_a[11] => ram_block1a4.PORTAADDR11
address_a[11] => ram_block1a5.PORTAADDR11
address_a[11] => ram_block1a6.PORTAADDR11
address_a[11] => ram_block1a7.PORTAADDR11
address_a[11] => ram_block1a8.PORTAADDR11
address_a[11] => ram_block1a9.PORTAADDR11
address_a[11] => ram_block1a10.PORTAADDR11
address_a[11] => ram_block1a11.PORTAADDR11
address_a[11] => ram_block1a12.PORTAADDR11
address_a[11] => ram_block1a13.PORTAADDR11
address_a[11] => ram_block1a14.PORTAADDR11
address_a[11] => ram_block1a15.PORTAADDR11
address_a[11] => ram_block1a16.PORTAADDR11
address_a[11] => ram_block1a17.PORTAADDR11
address_a[11] => ram_block1a18.PORTAADDR11
address_a[11] => ram_block1a19.PORTAADDR11
address_a[11] => ram_block1a20.PORTAADDR11
address_a[11] => ram_block1a21.PORTAADDR11
address_a[11] => ram_block1a22.PORTAADDR11
address_a[11] => ram_block1a23.PORTAADDR11
address_a[11] => ram_block1a24.PORTAADDR11
address_a[11] => ram_block1a25.PORTAADDR11
address_a[11] => ram_block1a26.PORTAADDR11
address_a[11] => ram_block1a27.PORTAADDR11
address_a[11] => ram_block1a28.PORTAADDR11
address_a[11] => ram_block1a29.PORTAADDR11
address_a[11] => ram_block1a30.PORTAADDR11
address_a[11] => ram_block1a31.PORTAADDR11
address_a[12] => address_reg_a[0].DATAIN
address_a[12] => decode_4oa:decode3.data[0]
address_a[12] => decode_4oa:deep_decode.data[0]
address_a[13] => address_reg_a[1].DATAIN
address_a[13] => decode_4oa:decode3.data[1]
address_a[13] => decode_4oa:deep_decode.data[1]
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
clock0 => ram_block1a18.CLK0
clock0 => ram_block1a19.CLK0
clock0 => ram_block1a20.CLK0
clock0 => ram_block1a21.CLK0
clock0 => ram_block1a22.CLK0
clock0 => ram_block1a23.CLK0
clock0 => ram_block1a24.CLK0
clock0 => ram_block1a25.CLK0
clock0 => ram_block1a26.CLK0
clock0 => ram_block1a27.CLK0
clock0 => ram_block1a28.CLK0
clock0 => ram_block1a29.CLK0
clock0 => ram_block1a30.CLK0
clock0 => ram_block1a31.CLK0
clock0 => address_reg_a[3].CLK
clock0 => address_reg_a[2].CLK
clock0 => address_reg_a[1].CLK
clock0 => address_reg_a[0].CLK
data_a[0] => ram_block1a0.PORTADATAIN
data_a[0] => ram_block1a8.PORTADATAIN
data_a[0] => ram_block1a16.PORTADATAIN
data_a[0] => ram_block1a24.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[1] => ram_block1a9.PORTADATAIN
data_a[1] => ram_block1a17.PORTADATAIN
data_a[1] => ram_block1a25.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[2] => ram_block1a10.PORTADATAIN
data_a[2] => ram_block1a18.PORTADATAIN
data_a[2] => ram_block1a26.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[3] => ram_block1a11.PORTADATAIN
data_a[3] => ram_block1a19.PORTADATAIN
data_a[3] => ram_block1a27.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[4] => ram_block1a12.PORTADATAIN
data_a[4] => ram_block1a20.PORTADATAIN
data_a[4] => ram_block1a28.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[5] => ram_block1a13.PORTADATAIN
data_a[5] => ram_block1a21.PORTADATAIN
data_a[5] => ram_block1a29.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[6] => ram_block1a14.PORTADATAIN
data_a[6] => ram_block1a22.PORTADATAIN
data_a[6] => ram_block1a30.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[7] => ram_block1a15.PORTADATAIN
data_a[7] => ram_block1a23.PORTADATAIN
data_a[7] => ram_block1a31.PORTADATAIN
q_a[0] <= mux_kib:mux2.result[0]
q_a[1] <= mux_kib:mux2.result[1]
q_a[2] <= mux_kib:mux2.result[2]
q_a[3] <= mux_kib:mux2.result[3]
q_a[4] <= mux_kib:mux2.result[4]
q_a[5] <= mux_kib:mux2.result[5]
q_a[6] <= mux_kib:mux2.result[6]
q_a[7] <= mux_kib:mux2.result[7]
wren_a => decode_4oa:decode3.enable


|kit_DE2|vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|decode_4oa:decode3
data[0] => w_anode244w[1].IN1
data[0] => w_anode260w[1].IN1
data[1] => w_anode252w[2].IN1
data[1] => w_anode260w[2].IN1
enable => w_anode231w[1].IN0
enable => w_anode244w[1].IN0
enable => w_anode252w[1].IN0
enable => w_anode260w[1].IN0
eq[0] <= w_anode231w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= w_anode244w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[2] <= w_anode252w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[3] <= w_anode260w[2].DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|decode_4oa:deep_decode
data[0] => w_anode244w[1].IN1
data[0] => w_anode260w[1].IN1
data[1] => w_anode252w[2].IN1
data[1] => w_anode260w[2].IN1
enable => w_anode231w[1].IN0
enable => w_anode244w[1].IN0
enable => w_anode252w[1].IN0
enable => w_anode260w[1].IN0
eq[0] <= w_anode231w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= w_anode244w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[2] <= w_anode252w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[3] <= w_anode260w[2].DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|mux_kib:mux2
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|vga_sync:VGA_khoi2
clock => clock~0.IN7
reset_n => reset_n~0.IN7
oVGA_CLK <= clock~0.DB_MAX_OUTPUT_PORT_TYPE
oVGA_BLANK <= D_FFs:V3.port3
oVGA_SYNC <= <GND>
oVGA_HS <= D_FFs:V1.port3
oVGA_VS <= D_FFs:V2.port3
Cursor_X[0] <= Cursor_X[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Cursor_X[1] <= Cursor_X[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Cursor_X[2] <= Cursor_X[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Cursor_X[3] <= Cursor_X[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Cursor_X[4] <= Cursor_X[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Cursor_X[5] <= Cursor_X[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Cursor_X[6] <= Cursor_X[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Cursor_X[7] <= Cursor_X[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Cursor_Y[0] <= Cursor_Y[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Cursor_Y[1] <= Cursor_Y[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Cursor_Y[2] <= Cursor_Y[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Cursor_Y[3] <= Cursor_Y[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Cursor_Y[4] <= Cursor_Y[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Cursor_Y[5] <= Cursor_Y[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Cursor_Y[6] <= Cursor_Y[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Cursor_Y[7] <= Cursor_Y[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
area_dislay <= D_FFs:B3.port3
area_reading <= D_FFs:B4.port3
done_dislay <= done_dislay~0.DB_MAX_OUTPUT_PORT_TYPE
done_dislay1 <= done_dislay1~0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|vga_sync:VGA_khoi2|D_FFs:V1
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|vga_sync:VGA_khoi2|D_FFs:V2
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|vga_sync:VGA_khoi2|D_FFs:V3
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|vga_sync:VGA_khoi2|D_FFs:A1
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|vga_sync:VGA_khoi2|D_FFs:A2
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|vga_sync:VGA_khoi2|D_FFs:B3
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|vga_sync:VGA_khoi2|D_FFs:B4
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|D_FFs:C2
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|D_FFs:C3
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|D_FFs:C4
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|D_FFs:C5
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|D_FFs:C6
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|D_FFs:C7
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|D_FFs:C8
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|D_FFs:C9
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|Khoi_phat_hien_canh_len:VGA_CONTROLLER
clock => clock~0.IN2
in => in~0.IN1
out <= out~0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|Khoi_phat_hien_canh_len:VGA_CONTROLLER|D_FFs:C10
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|Khoi_phat_hien_canh_len:VGA_CONTROLLER|D_FFs:C11
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2|D_FFs:C12
clock => out~reg0.CLK
reset_n => out~reg0.ACLR
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|SRAM_interface:BLOCK3
in_address[0] => oSRAM_ADDR[0].DATAIN
in_address[1] => oSRAM_ADDR[1].DATAIN
in_address[2] => oSRAM_ADDR[2].DATAIN
in_address[3] => oSRAM_ADDR[3].DATAIN
in_address[4] => oSRAM_ADDR[4].DATAIN
in_address[5] => oSRAM_ADDR[5].DATAIN
in_address[6] => oSRAM_ADDR[6].DATAIN
in_address[7] => oSRAM_ADDR[7].DATAIN