kit_de2.hier_info

VGA sourcecodes/documents

|kit_DE2
CLOCK_50 => clock.CLK
KEY[0] => reset.IN4
KEY[1] => KEY[1]~0.IN1
LEDR[0] <= control_wr_rd_for_SRAM:BLOCK4.wr_address_SRAM
LEDR[1] <= control_wr_rd_for_SRAM:BLOCK4.wr_address_SRAM
LEDR[2] <= control_wr_rd_for_SRAM:BLOCK4.wr_address_SRAM
LEDR[3] <= control_wr_rd_for_SRAM:BLOCK4.wr_address_SRAM
LEDR[4] <= control_wr_rd_for_SRAM:BLOCK4.wr_address_SRAM
LEDR[5] <= control_wr_rd_for_SRAM:BLOCK4.wr_address_SRAM
LEDR[6] <= control_wr_rd_for_SRAM:BLOCK4.wr_address_SRAM
LEDR[7] <= control_wr_rd_for_SRAM:BLOCK4.wr_address_SRAM
LEDR[8] <= control_wr_rd_for_SRAM:BLOCK4.wr_address_SRAM
LEDR[9] <= control_wr_rd_for_SRAM:BLOCK4.wr_address_SRAM
LEDR[10] <= control_wr_rd_for_SRAM:BLOCK4.wr_address_SRAM
LEDR[11] <= control_wr_rd_for_SRAM:BLOCK4.wr_address_SRAM
LEDR[12] <= control_wr_rd_for_SRAM:BLOCK4.wr_address_SRAM
LEDR[13] <= control_wr_rd_for_SRAM:BLOCK4.wr_address_SRAM
LEDR[14] <= control_wr_rd_for_SRAM:BLOCK4.wr_address_SRAM
LEDR[15] <= control_wr_rd_for_SRAM:BLOCK4.wr_address_SRAM
LEDR[16] <= control_wr_rd_for_SRAM:BLOCK4.wr_address_SRAM
LEDR[17] <= control_wr_rd_for_SRAM:BLOCK4.wr_address_SRAM
SW[0] => SW[0]~0.IN1
VGA_R[0] <= vga_controller:BLOCK2.vga_r
VGA_R[1] <= vga_controller:BLOCK2.vga_r
VGA_R[2] <= vga_controller:BLOCK2.vga_r
VGA_R[3] <= vga_controller:BLOCK2.vga_r
VGA_R[4] <= vga_controller:BLOCK2.vga_r
VGA_R[5] <= vga_controller:BLOCK2.vga_r
VGA_R[6] <= vga_controller:BLOCK2.vga_r
VGA_R[7] <= vga_controller:BLOCK2.vga_r
VGA_R[8] <= vga_controller:BLOCK2.vga_r
VGA_R[9] <= vga_controller:BLOCK2.vga_r
VGA_G[0] <= vga_controller:BLOCK2.vga_g
VGA_G[1] <= vga_controller:BLOCK2.vga_g
VGA_G[2] <= vga_controller:BLOCK2.vga_g
VGA_G[3] <= vga_controller:BLOCK2.vga_g
VGA_G[4] <= vga_controller:BLOCK2.vga_g
VGA_G[5] <= vga_controller:BLOCK2.vga_g
VGA_G[6] <= vga_controller:BLOCK2.vga_g
VGA_G[7] <= vga_controller:BLOCK2.vga_g
VGA_G[8] <= vga_controller:BLOCK2.vga_g
VGA_G[9] <= vga_controller:BLOCK2.vga_g
VGA_B[0] <= vga_controller:BLOCK2.vga_b
VGA_B[1] <= vga_controller:BLOCK2.vga_b
VGA_B[2] <= vga_controller:BLOCK2.vga_b
VGA_B[3] <= vga_controller:BLOCK2.vga_b
VGA_B[4] <= vga_controller:BLOCK2.vga_b
VGA_B[5] <= vga_controller:BLOCK2.vga_b
VGA_B[6] <= vga_controller:BLOCK2.vga_b
VGA_B[7] <= vga_controller:BLOCK2.vga_b
VGA_B[8] <= vga_controller:BLOCK2.vga_b
VGA_B[9] <= vga_controller:BLOCK2.vga_b
VGA_CLK <= vga_controller:BLOCK2.vga_clk
VGA_BLANK <= vga_controller:BLOCK2.vga_blank
VGA_SYNC <= vga_controller:BLOCK2.vga_sync
VGA_HS <= vga_controller:BLOCK2.vga_hs
VGA_VS <= vga_controller:BLOCK2.vga_vs
UART_RXD => UART_RXD~0.IN1
SRAM_ADDR[0] <= SRAM_interface:BLOCK3.oSRAM_ADDR
SRAM_ADDR[1] <= SRAM_interface:BLOCK3.oSRAM_ADDR
SRAM_ADDR[2] <= SRAM_interface:BLOCK3.oSRAM_ADDR
SRAM_ADDR[3] <= SRAM_interface:BLOCK3.oSRAM_ADDR
SRAM_ADDR[4] <= SRAM_interface:BLOCK3.oSRAM_ADDR
SRAM_ADDR[5] <= SRAM_interface:BLOCK3.oSRAM_ADDR
SRAM_ADDR[6] <= SRAM_interface:BLOCK3.oSRAM_ADDR
SRAM_ADDR[7] <= SRAM_interface:BLOCK3.oSRAM_ADDR
SRAM_ADDR[8] <= SRAM_interface:BLOCK3.oSRAM_ADDR
SRAM_ADDR[9] <= SRAM_interface:BLOCK3.oSRAM_ADDR
SRAM_ADDR[10] <= SRAM_interface:BLOCK3.oSRAM_ADDR
SRAM_ADDR[11] <= SRAM_interface:BLOCK3.oSRAM_ADDR
SRAM_ADDR[12] <= SRAM_interface:BLOCK3.oSRAM_ADDR
SRAM_ADDR[13] <= SRAM_interface:BLOCK3.oSRAM_ADDR
SRAM_ADDR[14] <= SRAM_interface:BLOCK3.oSRAM_ADDR
SRAM_ADDR[15] <= SRAM_interface:BLOCK3.oSRAM_ADDR
SRAM_ADDR[16] <= SRAM_interface:BLOCK3.oSRAM_ADDR
SRAM_ADDR[17] <= SRAM_interface:BLOCK3.oSRAM_ADDR
SRAM_DQ[0] <= SRAM_interface:BLOCK3.oSRAM_DQ
SRAM_DQ[1] <= SRAM_interface:BLOCK3.oSRAM_DQ
SRAM_DQ[2] <= SRAM_interface:BLOCK3.oSRAM_DQ
SRAM_DQ[3] <= SRAM_interface:BLOCK3.oSRAM_DQ
SRAM_DQ[4] <= SRAM_interface:BLOCK3.oSRAM_DQ
SRAM_DQ[5] <= SRAM_interface:BLOCK3.oSRAM_DQ
SRAM_DQ[6] <= SRAM_interface:BLOCK3.oSRAM_DQ
SRAM_DQ[7] <= SRAM_interface:BLOCK3.oSRAM_DQ
SRAM_DQ[8] <= SRAM_interface:BLOCK3.oSRAM_DQ
SRAM_DQ[9] <= SRAM_interface:BLOCK3.oSRAM_DQ
SRAM_DQ[10] <= SRAM_interface:BLOCK3.oSRAM_DQ
SRAM_DQ[11] <= SRAM_interface:BLOCK3.oSRAM_DQ
SRAM_DQ[12] <= SRAM_interface:BLOCK3.oSRAM_DQ
SRAM_DQ[13] <= SRAM_interface:BLOCK3.oSRAM_DQ
SRAM_DQ[14] <= SRAM_interface:BLOCK3.oSRAM_DQ
SRAM_DQ[15] <= SRAM_interface:BLOCK3.oSRAM_DQ
SRAM_WE_N <= SRAM_interface:BLOCK3.oSRAM_WE_N
SRAM_OE_N <= SRAM_interface:BLOCK3.oSRAM_OE_N
SRAM_UB_N <= SRAM_interface:BLOCK3.oSRAM_UB_N
SRAM_LB_N <= SRAM_interface:BLOCK3.oSRAM_LB_N
SRAM_CE_N <= SRAM_interface:BLOCK3.oSRAM_CE_N


|kit_DE2|async_receiver:BLOCK1
clk => Baud8GeneratorAcc[15].CLK
clk => Baud8GeneratorAcc[14].CLK
clk => Baud8GeneratorAcc[13].CLK
clk => Baud8GeneratorAcc[12].CLK
clk => Baud8GeneratorAcc[11].CLK
clk => Baud8GeneratorAcc[10].CLK
clk => Baud8GeneratorAcc[9].CLK
clk => Baud8GeneratorAcc[8].CLK
clk => Baud8GeneratorAcc[7].CLK
clk => Baud8GeneratorAcc[6].CLK
clk => Baud8GeneratorAcc[5].CLK
clk => Baud8GeneratorAcc[4].CLK
clk => Baud8GeneratorAcc[3].CLK
clk => Baud8GeneratorAcc[2].CLK
clk => Baud8GeneratorAcc[1].CLK
clk => Baud8GeneratorAcc[0].CLK
clk => RxD_sync_inv[1].CLK
clk => RxD_sync_inv[0].CLK
clk => RxD_cnt_inv[1].CLK
clk => RxD_cnt_inv[0].CLK
clk => RxD_bit_inv.CLK
clk => bit_spacing[3].CLK
clk => bit_spacing[2].CLK
clk => bit_spacing[1].CLK
clk => bit_spacing[0].CLK
clk => state[3].CLK
clk => state[2].CLK
clk => state[1].CLK
clk => state[0].CLK
clk => RxD_data[7]~reg0.CLK
clk => RxD_data[6]~reg0.CLK
clk => RxD_data[5]~reg0.CLK
clk => RxD_data[4]~reg0.CLK
clk => RxD_data[3]~reg0.CLK
clk => RxD_data[2]~reg0.CLK
clk => RxD_data[1]~reg0.CLK
clk => RxD_data[0]~reg0.CLK
clk => RxD_data_ready~reg0.CLK
clk => Baud8GeneratorAcc[16].CLK
RxD => RxD_sync_inv[0].DATAIN
RxD_data_ready <= RxD_data_ready~reg0.DB_MAX_OUTPUT_PORT_TYPE
RxD_data[0] <= RxD_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RxD_data[1] <= RxD_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RxD_data[2] <= RxD_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RxD_data[3] <= RxD_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RxD_data[4] <= RxD_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RxD_data[5] <= RxD_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RxD_data[6] <= RxD_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RxD_data[7] <= RxD_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|kit_DE2|vga_controller:BLOCK2
clock => clock~0.IN12
reset => reset~0.IN10
vga_clk <= vga_sync:VGA_khoi2.oVGA_CLK
vga_hs <= D_FFs:C5.port3
vga_vs <= D_FFs:C7.port3
vga_blank <= D_FFs:C3.port3
vga_sync <= vga_sync:VGA_khoi2.oVGA_SYNC
vga_r[0] <= D_FFs:C9.port3
vga_r[1] <= D_FFs:C9.port3
vga_r[2] <= vga_r~7.DB_MAX_OUTPUT_PORT_TYPE
vga_r[3] <= vga_r~6.DB_MAX_OUTPUT_PORT_TYPE
vga_r[4] <= vga_r~5.DB_MAX_OUTPUT_PORT_TYPE
vga_r[5] <= vga_r~4.DB_MAX_OUTPUT_PORT_TYPE
vga_r[6] <= vga_r~3.DB_MAX_OUTPUT_PORT_TYPE
vga_r[7] <= vga_r~2.DB_MAX_OUTPUT_PORT_TYPE
vga_r[8] <= vga_r~1.DB_MAX_OUTPUT_PORT_TYPE
vga_r[9] <= vga_r~0.DB_MAX_OUTPUT_PORT_TYPE
vga_b[0] <= D_FFs:C9.port3
vga_b[1] <= D_FFs:C9.port3
vga_b[2] <= vga_b~7.DB_MAX_OUTPUT_PORT_TYPE
vga_b[3] <= vga_b~6.DB_MAX_OUTPUT_PORT_TYPE
vga_b[4] <= vga_b~5.DB_MAX_OUTPUT_PORT_TYPE
vga_b[5] <= vga_b~4.DB_MAX_OUTPUT_PORT_TYPE
vga_b[6] <= vga_b~3.DB_MAX_OUTPUT_PORT_TYPE
vga_b[7] <= vga_b~2.DB_MAX_OUTPUT_PORT_TYPE
vga_b[8] <= vga_b~1.DB_MAX_OUTPUT_PORT_TYPE
vga_b[9] <= vga_b~0.DB_MAX_OUTPUT_PORT_TYPE
vga_g[0] <= D_FFs:C9.port3
vga_g[1] <= D_FFs:C9.port3
vga_g[2] <= vga_g~7.DB_MAX_OUTPUT_PORT_TYPE
vga_g[3] <= vga_g~6.DB_MAX_OUTPUT_PORT_TYPE
vga_g[4] <= vga_g~5.DB_MAX_OUTPUT_PORT_TYPE
vga_g[5] <= vga_g~4.DB_MAX_OUTPUT_PORT_TYPE
vga_g[6] <= vga_g~3.DB_MAX_OUTPUT_PORT_TYPE
vga_g[7] <= vga_g~2.DB_MAX_OUTPUT_PORT_TYPE
vga_g[8] <= vga_g~1.DB_MAX_OUTPUT_PORT_TYPE
vga_g[9] <= vga_g~0.DB_MAX_OUTPUT_PORT_TYPE
wr_address[0] => comb~13.DATAB
wr_address[1] => comb~12.DATAB
wr_address[2] => comb~11.DATAB
wr_address[3] => comb~10.DATAB
wr_address[4] => comb~9.DATAB
wr_address[5] => comb~8.DATAB
wr_address[6] => comb~7.DATAB
wr_address[7] => comb~6.DATAB
wr_address[8] => comb~5.DATAB
wr_address[9] => comb~4.DATAB
wr_address[10] => comb~3.DATAB
wr_address[11] => comb~2.DATAB
wr_address[12] => comb~1.DATAB
wr_address[13] => comb~0.DATAB
do_write => do_write~0.IN1
data_colour[0] => data_colour[0]~7.IN1
data_colour[1] => data_colour[1]~6.IN1
data_colour[2] => data_colour[2]~5.IN1
data_colour[3] => data_colour[3]~4.IN1
data_colour[4] => data_colour[4]~3.IN1
data_colour[5] => data_colour[5]~2.IN1
data_colour[6] => data_colour[6]~1.IN1
data_colour[7] => data_colour[7]~0.IN1
clear_do_read_on_SRAM => do_read_on_SRAM_in~2.OUTPUTSELECT
enable_do_read_on_SRAM => count_dislay~2.OUTPUTSELECT
enable_do_read_on_SRAM => count_dislay~3.OUTPUTSELECT
enable_do_read_on_SRAM => do_read_on_SRAM_in~1.OUTPUTSELECT
wr_request <= D_FFs:C12.port3
done_dislay1 <= vga_sync:VGA_khoi2.done_dislay1


|kit_DE2|vga_controller:BLOCK2|ram_vga:VGA_khoi1
address[0] => address[0]~13.IN1
address[1] => address[1]~12.IN1
address[2] => address[2]~11.IN1
address[3] => address[3]~10.IN1
address[4] => address[4]~9.IN1
address[5] => address[5]~8.IN1
address[6] => address[6]~7.IN1
address[7] => address[7]~6.IN1
address[8] => address[8]~5.IN1
address[9] => address[9]~4.IN1
address[10] => address[10]~3.IN1
address[11] => address[11]~2.IN1
address[12] => address[12]~1.IN1
address[13] => address[13]~0.IN1
clock => clock~0.IN1
data[0] => data[0]~7.IN1
data[1] => data[1]~6.IN1
data[2] => data[2]~5.IN1
data[3] => data[3]~4.IN1
data[4] => data[4]~3.IN1
data[5] => data[5]~2.IN1
data[6] => data[6]~1.IN1
data[7] => data[7]~0.IN1
wren => wren~0.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a


|kit_DE2|vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component
wren_a => altsyncram_4qc1:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_4qc1:auto_generated.data_a[0]
data_a[1] => altsyncram_4qc1:auto_generated.data_a[1]
data_a[2] => altsyncram_4qc1:auto_generated.data_a[2]
data_a[3] => altsyncram_4qc1:auto_generated.data_a[3]
data_a[4] => altsyncram_4qc1:auto_generated.data_a[4]
data_a[5] => altsyncram_4qc1:auto_generated.data_a[5]
data_a[6] => altsyncram_4qc1:auto_generated.data_a[6]
data_a[7] => altsyncram_4qc1:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_4qc1:auto_generated.address_a[0]
address_a[1] => altsyncram_4qc1:auto_generated.address_a[1]
address_a[2] => altsyncram_4qc1:auto_generated.address_a[2]
address_a[3] => altsyncram_4qc1:auto_generated.address_a[3]
address_a[4] => altsyncram_4qc1:auto_generated.address_a[4]
address_a[5] => altsyncram_4qc1:auto_generated.address_a[5]
address_a[6] => altsyncram_4qc1:auto_generated.address_a[6]
address_a[7] => altsyncram_4qc1:auto_generated.address_a[7]
address_a[8] => altsyncram_4qc1:auto_generated.address_a[8]
address_a[9] => altsyncram_4qc1:auto_generated.address_a[9]
address_a[10] => altsyncram_4qc1:auto_generated.address_a[10]
address_a[11] => altsyncram_4qc1:auto_generated.address_a[11]
address_a[12] => altsyncram_4qc1:auto_generated.address_a[12]
address_a[13] => altsyncram_4qc1:auto_generated.address_a[13]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_4qc1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_4qc1:auto_generated.q_a[0]
q_a[1] <= altsyncram_4qc1:auto_generated.q_a[1]
q_a[2] <= altsyncram_4qc1:auto_generated.q_a[2]
q_a[3] <= altsyncram_4qc1:auto_generated.q_a[3]
q_a[4] <= altsyncram_4qc1:auto_generated.q_a[4]
q_a[5] <= altsyncram_4qc1:auto_generated.q_a[5]
q_a[6] <= altsyncram_4qc1:auto_generated.q_a[6]
q_a[7] <= altsyncram_4qc1:auto_generated.q_a[7]
q_b[0] <= <GND>


|kit_DE2|vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR