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📄 mux_kib.tdf

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--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=4 LPM_WIDTH=8 LPM_WIDTHS=2 data result sel
--VERSION_BEGIN 6.0 cbx_lpm_mux 2006:01:09:11:16:16:SJ cbx_mgl 2006:04:14:11:14:36:SJ  VERSION_END


--  Copyright (C) 1991-2006 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 16 
SUBDESIGN mux_kib
( 
	data[31..0]	:	input;
	result[7..0]	:	output;
	sel[1..0]	:	input;
) 
VARIABLE 
	result_node[7..0]	: WIRE;
	sel_node[1..0]	: WIRE;
	w_data272w[3..0]	: WIRE;
	w_data302w[3..0]	: WIRE;
	w_data327w[3..0]	: WIRE;
	w_data352w[3..0]	: WIRE;
	w_data377w[3..0]	: WIRE;
	w_data402w[3..0]	: WIRE;
	w_data427w[3..0]	: WIRE;
	w_data452w[3..0]	: WIRE;
	w_result284w	: WIRE;
	w_result314w	: WIRE;
	w_result339w	: WIRE;
	w_result364w	: WIRE;
	w_result389w	: WIRE;
	w_result414w	: WIRE;
	w_result439w	: WIRE;
	w_result464w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( (((w_data452w[1..1] & sel_node[0..0]) & (! w_result464w)) # (w_result464w & (w_data452w[3..3] # (! sel_node[0..0])))), (((w_data427w[1..1] & sel_node[0..0]) & (! w_result439w)) # (w_result439w & (w_data427w[3..3] # (! sel_node[0..0])))), (((w_data402w[1..1] & sel_node[0..0]) & (! w_result414w)) # (w_result414w & (w_data402w[3..3] # (! sel_node[0..0])))), (((w_data377w[1..1] & sel_node[0..0]) & (! w_result389w)) # (w_result389w & (w_data377w[3..3] # (! sel_node[0..0])))), (((w_data352w[1..1] & sel_node[0..0]) & (! w_result364w)) # (w_result364w & (w_data352w[3..3] # (! sel_node[0..0])))), (((w_data327w[1..1] & sel_node[0..0]) & (! w_result339w)) # (w_result339w & (w_data327w[3..3] # (! sel_node[0..0])))), (((w_data302w[1..1] & sel_node[0..0]) & (! w_result314w)) # (w_result314w & (w_data302w[3..3] # (! sel_node[0..0])))), (((w_data272w[1..1] & sel_node[0..0]) & (! w_result284w)) # (w_result284w & (w_data272w[3..3] # (! sel_node[0..0])))));
	sel_node[] = ( sel[1..0]);
	w_data272w[] = ( data[24..24], data[16..16], data[8..8], data[0..0]);
	w_data302w[] = ( data[25..25], data[17..17], data[9..9], data[1..1]);
	w_data327w[] = ( data[26..26], data[18..18], data[10..10], data[2..2]);
	w_data352w[] = ( data[27..27], data[19..19], data[11..11], data[3..3]);
	w_data377w[] = ( data[28..28], data[20..20], data[12..12], data[4..4]);
	w_data402w[] = ( data[29..29], data[21..21], data[13..13], data[5..5]);
	w_data427w[] = ( data[30..30], data[22..22], data[14..14], data[6..6]);
	w_data452w[] = ( data[31..31], data[23..23], data[15..15], data[7..7]);
	w_result284w = (((w_data272w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data272w[2..2])));
	w_result314w = (((w_data302w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data302w[2..2])));
	w_result339w = (((w_data327w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data327w[2..2])));
	w_result364w = (((w_data352w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data352w[2..2])));
	w_result389w = (((w_data377w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data377w[2..2])));
	w_result414w = (((w_data402w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data402w[2..2])));
	w_result439w = (((w_data427w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data427w[2..2])));
	w_result464w = (((w_data452w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data452w[2..2])));
END;
--VALID FILE

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