vga_sync.v

VGA sourcecodes/documents

module	vga_sync( 	  clock,
					  reset_n,
					/////////////////////////
					  oVGA_CLK,
					  oVGA_BLANK,
					  oVGA_SYNC,
					  oVGA_HS,
					  oVGA_VS,
					//////////////////////////
					  Cursor_X,
					  Cursor_Y,
					//////////////////////////
					  area_dislay,
					  area_reading,
					  done_dislay,
					  done_dislay1
					
			    );
 
input	clock;
input 	reset_n;

 reg [9:0]H_Cont;
 reg [9:0]V_Cont;

output	reg [7:0]Cursor_X,Cursor_Y;
output	oVGA_CLK;
output	oVGA_BLANK;
output	oVGA_SYNC;
output	oVGA_HS;
output	oVGA_VS;
output	area_dislay,area_reading,done_dislay,done_dislay1;

//////////////////////////////////////////////////////////////
assign	oVGA_SYNC = 1'b0;
assign	oVGA_CLK = clock;

wire 	oVGA_HS_in = (H_Cont >= 655 && H_Cont < 751 ) ? 1'b0 : 1'b1 ;
wire 	oVGA_VS_in = (V_Cont >= 489 && V_Cont < 491 ) ? 1'b0 : 1'b1 ;
wire 	oVGA_BLANK_in = oVGA_HS_in & oVGA_VS_in;
D_FFs 	V1	(clock,reset_n,oVGA_HS_in,oVGA_HS );
D_FFs 	V2	(clock,reset_n,oVGA_VS_in,oVGA_VS );
D_FFs 	V3	(clock,reset_n,oVGA_BLANK_in,oVGA_BLANK);
/////////////////////////////////////////////////////////////
always @ (posedge clock or negedge reset_n)
	begin
		if (!reset_n)
			begin
			 	H_Cont <= 10'd0 ;
			end
		else
			begin
				if(enable_H_Cont == 1'b1)
				   H_Cont <= 10'd0 ;
				else 
				   H_Cont <= H_Cont + 1'b1;
			end
	end

wire	enable_H_Cont_in,enable_H_Cont;
assign	enable_H_Cont_in = (H_Cont == 798) ? 1'b1 : 1'b0;
D_FFs	A1(clock,reset_n,enable_H_Cont_in,enable_H_Cont);
/////////////////////////////////////////////////////////////
always @ (posedge clock or negedge reset_n)
	begin
		if (!reset_n)
			begin
				V_Cont <= 10'd0;
			end
		else
			begin
				if (enable_V_Cont == 1'b1)
					V_Cont <= 0 ;
				 else if (enable_H_Cont)
					V_Cont <= V_Cont +1'b1;			
			end
	end

wire	enable_V_Cont_in,enable_V_Cont;
assign	enable_V_Cont_in = (enable_H_Cont_in && V_Cont == 524) ? 1'b1 : 1'b0 ;	
D_FFs 	A2	(clock,reset_n,enable_V_Cont_in,enable_V_Cont);

///////////////////////////////////////////////////////////////////////
wire	area_dislay_in = (H_Cont >=  191 && H_Cont < 445 &&
					   	  V_Cont >=  111 && V_Cont < 365) ? 1'b1 : 1'b0 ;
wire area_dislay;
D_FFs 	B3	(clock,reset_n,area_dislay_in,area_dislay);	

//////////////////////////////////////////////////////////////////////
wire	area_read_in = (V_Cont >=  100 && V_Cont < 375) ? 1'b1 : 1'b0 ;
wire 	area_reading;
D_FFs 	B4	(clock,reset_n,area_read_in,area_reading);
assign	done_dislay = (H_Cont == 455 && V_Cont == 375) ? 1'b1 : 1'b0;
assign	done_dislay1 = (H_Cont == 456 && V_Cont == 375) ? 1'b1 : 1'b0;
		
////////////////////////////////////////////////////////////////////////
wire	[7:0] Cursor_X_in = H_Cont  - 190;
wire	[7:0] Cursor_Y_in = V_Cont  - 110;

always @ (posedge clock or negedge reset_n)
	begin
		if(!reset_n)
			begin
				Cursor_X <= 8'd0; 
				Cursor_Y <= 8'd0;
			end
		else
			if (area_dislay_in)		
				begin
					Cursor_X <= Cursor_X_in;
					Cursor_Y <= Cursor_Y_in;
				end
			else	
				begin
					Cursor_X <= 8'd0 ;
					Cursor_Y <= 8'd0 ;
				end
	end					
endmodule	

/////////////////////////////////////////////////////////////////////////////	
module  D_FFs (clock,reset_n,in,out);

	input	clock;
	input 	reset_n;
	input	in;
	
	output	reg out;
	always @ (posedge clock or negedge reset_n)
		begin
			if (!reset_n)
				out <= 1'b0;
			else
				out <= in ;
		end
endmodule