processing_image_0.v

VGA sourcecodes/documents

module	Processing_image_0 (	clock,
								reset,
								register1,
								register2,
								register3,
								register4,
								register5,
								register6,
								register7,
								register8,
								register9,
								out
						  );
	input	clock;
	input 	reset;
	
	input	[7:0]register1;
	input	[7:0]register2;
	input	[7:0]register3;
	input	[7:0]register4;
	input	[7:0]register5;
	input	[7:0]register6;
	input	[7:0]register7;
	input	[7:0]register8;
	input	[7:0]register9;
	
	output	[12:0]out;

///////////////// multiplex with filter window 3*3 /////////////////////
	reg	[10:0]multi_1;
	reg	[10:0]multi_2;
	reg	[10:0]multi_3;
	reg	[10:0]multi_4;
	
	reg	[10:0]multi_6;
	reg	[10:0]multi_7;
	reg	[10:0]multi_8;
	reg	[10:0]multi_9;

/*
	 k = 0: [10:0] = 0;
	 k = 1: [10:0] = {3'b000,register};
	 k = 2: [10:0] = {2'b00,register,1'b0};
	 k =-1: [10:0] = ~{3'b000,register} + 1;
	 k =-2: [10:0] = ~{2'b00,register,1'b0} + 1;			
*/	
always @ (posedge clock or negedge reset)						
	begin
		if (!reset)
			begin
				multi_1 <= 0;
				multi_2 <= 0;
				multi_3 <= 0;
				multi_4 <= 0;
				
				multi_6 <= 0;
				multi_7 <= 0;
				multi_8 <= 0;
				multi_9 <= 0;
			end
		else
			begin
				multi_1 <= {3'b000,register1};
				multi_2 <= {2'b00,register2,1'b0};
				multi_3 <= {3'b000,register3};
				multi_4 <= 0;
				
				multi_6 <= 0;
				multi_7 <= ~{3'b000,register7} + 11'd1;
				multi_8 <= ~{2'b00,register8,1'b0} + 11'd1;			
				multi_9 <= ~{3'b000,register9} + 11'd1;
			end	
	end

//////////////////////  Add floor 1st  ////////////////////
	reg	[11:0] add_1_1;
	reg	[11:0] add_1_2;
	reg	[11:0] add_1_3;
	reg	[11:0] add_1_4;
	
	wire	[11:0]add_1_1_1 = {multi_1[10],multi_1};
	wire	[11:0]add_1_1_2 = {multi_2[10],multi_2};
	wire	[11:0]add_1_2_1 = {multi_3[10],multi_3};
	wire	[11:0]add_1_2_2 = {multi_4[10],multi_4};
	wire	[11:0]add_1_3_1 = {multi_6[10],multi_6};
	wire	[11:0]add_1_3_2 = {multi_7[10],multi_7};
	wire	[11:0]add_1_4_1 = {multi_8[10],multi_8};
	wire	[11:0]add_1_4_2 = {multi_9[10],multi_9};
	
always @ (posedge clock or negedge reset)
	begin
		if (!reset)
			begin
				add_1_1 <= 0;
				add_1_2 <= 0;
				add_1_3 <= 0;
				add_1_4 <= 0;
			end
		else
			begin
				add_1_1 <= add_1_1_1 + add_1_1_2;
				add_1_2 <= add_1_2_1 + add_1_2_2;
				add_1_3 <= add_1_3_1 + add_1_3_2;
				add_1_4 <= add_1_4_1 + add_1_4_2;
			end
	end
	
//////////////// add floor 2nd /////////////////////////////////////
	reg	[12:0]add_2_1;
	reg [12:0]add_2_2;
	
	wire	[12:0]add_2_1_1 = {add_1_1[11],add_1_1};
	wire	[12:0]add_2_1_2 = {add_1_2[11],add_1_2};
	wire	[12:0]add_2_2_1 = {add_1_3[11],add_1_3};
	wire	[12:0]add_2_2_2 = {add_1_4[11],add_1_4};

always @ (posedge clock or negedge reset)
	begin
		if (!reset)
			begin
				add_2_1 <= 0;
				add_2_2 <= 0;
			end
		else
			begin
				add_2_1 <= add_2_1_1 + add_2_1_2;
				add_2_2 <= add_2_2_1 + add_2_2_2;
			end
	end

///////////////// add floor 3th //////////////////////////////////////
	reg	[13:0]add_3;
	
	wire	[13:0]add_3_1 = {add_2_1[12],add_2_1};
	wire	[13:0]add_3_2 = {add_2_2[12],add_2_2};
	
always @ (posedge clock or negedge reset)
	begin
		if (!reset)
			add_3 <= 0;
		else
			add_3 <= add_3_1 + add_3_2;
	end
	
/////////////// take absolute value ////////////////////////////////////
	wire	flag_abs = add_3[13];
	reg	[12:0]abs;
always @ (posedge clock or negedge reset)
	begin
		if (!reset)
			 abs <= 0;
		else
			begin
				if (flag_abs)
					abs <= ~add_3[12:0] + 13'd1;
				else
					abs <= add_3[12:0];
			end
	end
	
assign	out = abs;
	
endmodule