vga_controller.v

VGA sourcecodes/documents

module	vga_controller 	 (	clock,
							reset,
							///// interface VGA ///////
							vga_clk,
							vga_hs,
							vga_vs,
							vga_blank,
							vga_sync,
							vga_r,
							vga_b,
							vga_g,
							///// out signal for VGA_Ram ////////
							wr_address,
							do_write,
							data_colour,
							clear_do_read_on_SRAM,
							enable_do_read_on_SRAM,
							///// out signal for SRAM_Controller ////////
							wr_request,
							done_dislay1
					  );
	input	clock;
	input	reset;
	
	//input	set_wr_request_from_SRAM;
	input	clear_do_read_on_SRAM;
	input	enable_do_read_on_SRAM;
	
	output	vga_clk;
	output	vga_hs;
	output	vga_vs;
	output 	vga_blank;
	output	vga_sync;
	output	[9:0]vga_r;
	output	[9:0]vga_g;
	output	[9:0]vga_b;
	
	input	[13:0]wr_address;
	input	do_write;
	input	[7:0]data_colour;
	
	output	wr_request;
	output	done_dislay1;
	
	wire	[7:0]q;
	ram_vga VGA_khoi1(
						.address(address),
						.data(data_colour),
						.clock(clock),
						.wren(do_write),
						.q(q)
					  );
					
	vga_sync	VGA_khoi2( 	  .clock(clock),
							  .reset_n(reset),
							/////////////////////////
							  .oVGA_CLK(vga_clk),
							  .oVGA_BLANK(blank),
							  .oVGA_SYNC(vga_sync),
							  .oVGA_HS(hs),
							  .oVGA_VS(vs),
							//////////////////////////
							  .Cursor_X(Cursor_X),
							  .Cursor_Y(Cursor_Y),
							//////////////////////////
							  .area_dislay(area_dislay),
							  .area_reading(area_reading),
							  .done_dislay(done_dislay),
							  .done_dislay1(done_dislay1)
					     );
	wire	[7:0]Cursor_X,Cursor_Y;	
	wire	area_dislay;			
	wire	done_dislay;				
	wire	area_reading;
	
	////////////// create address for Ram_VGA /////////////////////
	wire	[13:0]rd_address = {Cursor_Y[7:1],Cursor_X[7:1]};
	wire	[13:0]address = do_write ? wr_address : rd_address;
		
	//////////////// data write for Ram VGA ///////////////////////					
	wire	[7:0]data_vga = q;
	
	assign	vga_r = area_dislay2 ? {data_vga,2'b11} : 10'd0;
	assign	vga_g = area_dislay2 ? {data_vga,2'b11} : 10'd0;
	assign	vga_b = area_dislay2 ? {data_vga,2'b11} : 10'd0;
	
	wire	blank,blank1;
	wire	hs,hs1;
	wire	vs,vs1;
	
	D_FFs 	C2	(clock,reset,blank,blank1);
	D_FFs 	C3	(clock,reset,blank1,vga_blank);

	D_FFs 	C4	(clock,reset,hs,hs1);
	D_FFs 	C5	(clock,reset,hs1,vga_hs);
	
	D_FFs 	C6	(clock,reset,vs,vs1);
	D_FFs 	C7	(clock,reset,vs1,vga_vs);

	wire	area_dislay1,area_dislay2;
	
	D_FFs 	C8	(clock,reset,area_dislay,area_dislay1);
	D_FFs 	C9	(clock,reset,area_dislay1,area_dislay2);
	
	// after 15/60s  meaning after 4 signal done_dislay active //
	// then signal wr_request_in active //
	reg	[1:0] count_dislay;
	always @ (posedge clock or negedge reset)
		begin
			if(! reset)
				count_dislay <= 2'b00;
			else
				begin
					if(enable_count_dislay)
						begin
							if(done_dislay)
								count_dislay <= count_dislay + 1'b1;
							end
					else
						count_dislay <= 2'b00;
				end
		end
		
	wire	flag_do_read_on_SRAM = (count_dislay == 2'b00) ? 1'b1 : 1'b0;
	wire	enable_count_dislay = enable_do_read_on_SRAM;
	wire	set_do_read_on_SRAM;
	
	Khoi_phat_hien_canh_len VGA_CONTROLLER(clock,flag_do_read_on_SRAM,set_do_read_on_SRAM);
	
	reg		do_read_on_SRAM_in;
	always @ (posedge clock or negedge reset)
		begin
			if(! reset)
				do_read_on_SRAM_in <= 0;
			else
				begin
					if (clear_do_read_on_SRAM)
						do_read_on_SRAM_in <= 0;
					else 
						begin
							if (enable_do_read_on_SRAM )
								begin
									if (set_do_read_on_SRAM)
										do_read_on_SRAM_in <= 1;
									else;	
								end		
							else
								do_read_on_SRAM_in <= 0;
						end
				end
		end
	
	wire	wr_request_in = do_read_on_SRAM_in & ~area_reading ;	
	D_FFs 	C12	(clock,reset,wr_request_in,wr_request);
	
endmodule

/////////////////////////////////////////////////////////////////////////////
module	Khoi_phat_hien_canh_len (clock,in,out);

 input 	clock;
 input 	in;
 output	out;

 wire	temp1,temp2;

D_FFs 	C10	(clock,1'b1,in,temp1);
D_FFs 	C11	(clock,1'b1,temp1,temp2);

assign	out = (~temp2 && temp1) ? 1'b1 : 1'b0;

endmodule