khoi_fifo.v

VGA sourcecodes/documents

module	Khoi_FIFO (
					clock,
					reset,
					/////////////////////////
					data_from_UART,
					data_ready_from_UART,
					/////////////////////////
					signal_data_valid,
					/////// 9 reg for BLOCK processing //////
					register1,
					register2,
					register3,
					register4,
					register5,
					register6,
					register7,
					register8,
					register9 
				   );
	input	clock;
	input	reset;
	
	input	[7:0]data_from_UART;
	input	data_ready_from_UART;
	
	output	reg signal_data_valid;
	
	output	reg[7:0]register1;
	output	reg[7:0]register2;
	output	reg[7:0]register3;
	output	reg[7:0]register4;
	output	reg[7:0]register5;
	output	reg[7:0]register6;
	output	reg[7:0]register7;
	output	reg[7:0]register8;
	output	reg[7:0]register9;
	
	wire	[7:0]q0,q1;
	wire	[7:0]register1_in = register2;
	wire	[7:0]register2_in = register3;
	wire	[7:0]register3_in = q0;
	wire	[7:0]register4_in = register5;
	wire	[7:0]register5_in = register6;
	wire	[7:0]register6_in = q1;
	wire	[7:0]register7_in = register8;
	wire	[7:0]register8_in = register9;
	wire	[7:0]register9_in = data_from_UART;
	
	wire	flag_data_ready_from_UART;
	Khoi_phat_hien_canh_len (clock,data_ready_from_UART,flag_data_ready_from_UART);
	
	FIFO_Image BLOCK_FIFO_0 (
					.clock(clock),
					.data(q1),
					.rdreq(data_ready_from_UART0),
					.wrreq(data_ready_from_UART0),
					.q(q0));
					
	FIFO_Image BLOCK_FIFO_1 (
					.clock(clock),
					.data(data_from_UART),
					.rdreq(data_ready_from_UART),
					.wrreq(data_ready_from_UART),
					.q(q1));
	
	always @ (posedge clock)
		begin
			if (data_ready_from_UART1)
				begin
					register1 <= register1_in;
					register2 <= register2_in;
					register3 <= register3_in;
					register4 <= register4_in;
					register5 <= register5_in;
					register6 <= register6_in;
					register7 <= register7_in;
					register8 <= register8_in;
					register9 <= register9_in;
				end
			else;
		end
		
	reg		data_ready_from_UART0,data_ready_from_UART1;
	wire	signal_data_valid_in = data_ready_from_UART1 ;
	
always @ (posedge clock)
	begin
		data_ready_from_UART0 <= flag_data_ready_from_UART;
		data_ready_from_UART1 <= data_ready_from_UART0;
	end
		
reg	[7:0]count_temp;
	always @ (posedge clock or negedge reset)
		begin	
			if (! reset)
				count_temp <= 0;
			else
				begin
					if (enable_count_temp)
						count_temp <= count_temp + 8'd1;
					else;
				end
		end
	
	wire	enable_valid = (count_temp == 130) ? 1'b1 : 1'b0;
	wire	enable_count_temp = ~enable_valid & data_ready_from_UART0;
	
	always @(posedge clock or negedge reset)
		begin
			if (!reset)
				signal_data_valid <= 0;
			else
				begin
					if (enable_valid)
						signal_data_valid <= signal_data_valid_in;
					else
						signal_data_valid <= 0;
				end
		end												
	
endmodule