kit_de2.map.rpt

VGA sourcecodes/documents

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+-----------------+
; Name                                                                                                                                                                     ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size   ; MIF             ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+-----------------+
; Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_0|scfifo:scfifo_component|scfifo_1eu:auto_generated|a_dpfifo_8ku:dpfifo|dpram_4it:FIFOram|altsyncram_6sj1:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 128          ; 8            ; 128          ; 8            ; 1024   ; None            ;
; Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_1|scfifo:scfifo_component|scfifo_1eu:auto_generated|a_dpfifo_8ku:dpfifo|dpram_4it:FIFOram|altsyncram_6sj1:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 128          ; 8            ; 128          ; 8            ; 1024   ; None            ;
; vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated|ALTSYNCRAM                                                        ; AUTO ; Single Port      ; 16384        ; 8            ; --           ; --           ; 131072 ; copy_lena_3.hex ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+-----------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |kit_DE2|control_wr_rd_for_SRAM:BLOCK4|current_state                                                                                                            ;
+-------------------------------------+-------------------------------------+------------------------------------+--------------------------------+-------------------------------+
; Name                                ; current_state.Buffer_data_High_full ; current_state.Buffer_data_Low_full ; current_state.Wait_buffer_High ; current_state.Wait_buffer_Low ;
+-------------------------------------+-------------------------------------+------------------------------------+--------------------------------+-------------------------------+
; current_state.Wait_buffer_Low       ; 0                                   ; 0                                  ; 0                              ; 0                             ;
; current_state.Wait_buffer_High      ; 0                                   ; 0                                  ; 1                              ; 1                             ;
; current_state.Buffer_data_Low_full  ; 0                                   ; 1                                  ; 0                              ; 1                             ;
; current_state.Buffer_data_High_full ; 1                                   ; 0                                  ; 0                              ; 1                             ;
+-------------------------------------+-------------------------------------+------------------------------------+--------------------------------+-------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 614   ;
; Number of registers using Synchronous Clear  ; 35    ;
; Number of registers using Synchronous Load   ; 25    ;
; Number of registers using Asynchronous Clear ; 444   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 225   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------+
; 3:1                ; 18 bits   ; 36 LEs        ; 18 LEs               ; 18 LEs                 ; Yes        ; |kit_DE2|control_wr_rd_for_SRAM:BLOCK4|in_address[12] ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |kit_DE2|async_receiver:BLOCK1|bit_spacing[2]         ;
; 3:1                ; 2 bits    ; 4 LEs         ; 0 LEs                ; 4 LEs                  ; Yes        ; |kit_DE2|async_receiver:BLOCK1|RxD_cnt_inv[0]         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                              ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                               ;
+---------------------------------+--------------------+------+-----------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_0|scfifo:scfifo_component|scfifo_1eu:auto_generated|a_dpfifo_8ku:dpfifo|dpram_4it:FIFOram|altsyncram_6sj1:altsyncram2 ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                     ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                      ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_1|scfifo:scfifo_component|scfifo_1eu:auto_generated|a_dpfifo_8ku:dpfifo|dpram_4it:FIFOram|altsyncram_6sj1:altsyncram2 ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                     ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                      ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: async_receiver:BLOCK1 ;
+------------------------+----------+--------------------------------+
; Parameter Name         ; Value    ; Type                           ;
+------------------------+----------+--------------------------------+
; ClkFrequency           ; 25000000 ; Integer                        ;
; Baud                   ; 115200   ; Integer                        ;
; Baud8                  ; 921600   ; Integer                        ;
; Baud8GeneratorAccWidth ; 16       ; Integer                        ;
+------------------------+----------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component ;
+------------------------------------+-----------------+---------------------------------------------------------------+
; Parameter Name                     ; Value           ; Type                                                          ;