kit_de2.map.rpt

VGA sourcecodes/documents

; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Optimization Technique -- Cyclone II                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Remove Duplicate Logic                                             ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M4K Memory Blocks                                ; Unlimited          ; Unlimited          ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                     ;
+----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                                           ;
+----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------------------------------+
; FIFO_Image.v                     ; yes             ; User Verilog HDL File        ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/FIFO_Image.v             ;
; asyn_receiver.v                  ; yes             ; User Verilog HDL File        ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/asyn_receiver.v          ;
; control_wr_rd_for_SRAM.v         ; yes             ; User Verilog HDL File        ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/control_wr_rd_for_SRAM.v ;
; Khoi_FIFO.v                      ; yes             ; User Verilog HDL File        ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/Khoi_FIFO.v              ;
; kit_DE2.v                        ; yes             ; User Verilog HDL File        ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/kit_DE2.v                ;
; Processing_image.v               ; yes             ; User Verilog HDL File        ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/Processing_image.v       ;
; Processing_image_0.v             ; yes             ; User Verilog HDL File        ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/Processing_image_0.v     ;
; Processing_image_1.v             ; yes             ; User Verilog HDL File        ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/Processing_image_1.v     ;
; ram_vga.v                        ; yes             ; User Verilog HDL File        ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/ram_vga.v                ;
; SRAM_interface.v                 ; yes             ; User Verilog HDL File        ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/SRAM_interface.v         ;
; vga_controller.v                 ; yes             ; User Verilog HDL File        ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/vga_controller.v         ;
; vga_sync.v                       ; yes             ; User Verilog HDL File        ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/vga_sync.v               ;
; altsyncram.tdf                   ; yes             ; Megafunction                 ; e:/chuong_trinh/quartusii/libraries/megafunctions/altsyncram.tdf                                       ;
; stratix_ram_block.inc            ; yes             ; Other                        ; e:/chuong_trinh/quartusii/libraries/megafunctions/stratix_ram_block.inc                                ;
; lpm_mux.inc                      ; yes             ; Other                        ; e:/chuong_trinh/quartusii/libraries/megafunctions/lpm_mux.inc                                          ;
; lpm_decode.inc                   ; yes             ; Other                        ; e:/chuong_trinh/quartusii/libraries/megafunctions/lpm_decode.inc                                       ;
; aglobal60.inc                    ; yes             ; Other                        ; e:/chuong_trinh/quartusii/libraries/megafunctions/aglobal60.inc                                        ;
; altsyncram.inc                   ; yes             ; Other                        ; e:/chuong_trinh/quartusii/libraries/megafunctions/altsyncram.inc                                       ;
; a_rdenreg.inc                    ; yes             ; Other                        ; e:/chuong_trinh/quartusii/libraries/megafunctions/a_rdenreg.inc                                        ;
; altrom.inc                       ; yes             ; Other                        ; e:/chuong_trinh/quartusii/libraries/megafunctions/altrom.inc                                           ;
; altram.inc                       ; yes             ; Other                        ; e:/chuong_trinh/quartusii/libraries/megafunctions/altram.inc                                           ;
; altdpram.inc                     ; yes             ; Other                        ; e:/chuong_trinh/quartusii/libraries/megafunctions/altdpram.inc                                         ;
; altqpram.inc                     ; yes             ; Other                        ; e:/chuong_trinh/quartusii/libraries/megafunctions/altqpram.inc                                         ;
; db/altsyncram_4qc1.tdf           ; yes             ; Auto-Generated Megafunction  ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/altsyncram_4qc1.tdf   ;
; db/decode_4oa.tdf                ; yes             ; Auto-Generated Megafunction  ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/decode_4oa.tdf        ;
; db/mux_kib.tdf                   ; yes             ; Auto-Generated Megafunction  ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/mux_kib.tdf           ;
; scfifo.tdf                       ; yes             ; Megafunction                 ; e:/chuong_trinh/quartusii/libraries/megafunctions/scfifo.tdf                                           ;
; a_regfifo.inc                    ; yes             ; Other                        ; e:/chuong_trinh/quartusii/libraries/megafunctions/a_regfifo.inc                                        ;
; a_dpfifo.inc                     ; yes             ; Other                        ; e:/chuong_trinh/quartusii/libraries/megafunctions/a_dpfifo.inc                                         ;
; a_i2fifo.inc                     ; yes             ; Other                        ; e:/chuong_trinh/quartusii/libraries/megafunctions/a_i2fifo.inc                                         ;
; a_fffifo.inc                     ; yes             ; Other                        ; e:/chuong_trinh/quartusii/libraries/megafunctions/a_fffifo.inc                                         ;
; a_f2fifo.inc                     ; yes             ; Other                        ; e:/chuong_trinh/quartusii/libraries/megafunctions/a_f2fifo.inc                                         ;
; db/scfifo_1eu.tdf                ; yes             ; Auto-Generated Megafunction  ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/scfifo_1eu.tdf        ;
; db/a_dpfifo_8ku.tdf              ; yes             ; Auto-Generated Megafunction  ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/a_dpfifo_8ku.tdf      ;
; db/a_fefifo_u7e.tdf              ; yes             ; Auto-Generated Megafunction  ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/a_fefifo_u7e.tdf      ;
; db/cntr_sj7.tdf                  ; yes             ; Auto-Generated Megafunction  ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/cntr_sj7.tdf          ;
; db/dpram_4it.tdf                 ; yes             ; Auto-Generated Megafunction  ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/dpram_4it.tdf         ;
; db/altsyncram_6sj1.tdf           ; yes             ; Auto-Generated Megafunction  ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/altsyncram_6sj1.tdf   ;
; db/cntr_el8.tdf                  ; yes             ; Auto-Generated Megafunction  ; C:/Documents and Settings/GIAP CUI/Desktop/LVTN/Verilog_project/Final_project/db/cntr_el8.tdf          ;
+----------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------------------------------------+


+------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary          ;
+---------------------------------------------+--------+
; Resource                                    ; Usage  ;
+---------------------------------------------+--------+
; Estimated Total logic elements              ; 614    ;
; Total combinational functions               ; 477    ;