kit_de2.map.rpt

VGA sourcecodes/documents

Analysis & Synthesis report for kit_DE2
Sat May 31 20:21:14 2008
Version 6.0 Build 178 04/27/2006 SJ Web Edition


---------------------
; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |kit_DE2|control_wr_rd_for_SRAM:BLOCK4|current_state
  9. General Register Statistics
 10. Multiplexer Restructuring Statistics (Restructuring Performed)
 11. Source assignments for vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component|altsyncram_4qc1:auto_generated
 12. Source assignments for Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_0|scfifo:scfifo_component|scfifo_1eu:auto_generated|a_dpfifo_8ku:dpfifo|dpram_4it:FIFOram|altsyncram_6sj1:altsyncram2
 13. Source assignments for Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_1|scfifo:scfifo_component|scfifo_1eu:auto_generated|a_dpfifo_8ku:dpfifo|dpram_4it:FIFOram|altsyncram_6sj1:altsyncram2
 14. Parameter Settings for User Entity Instance: async_receiver:BLOCK1
 15. Parameter Settings for User Entity Instance: vga_controller:BLOCK2|ram_vga:VGA_khoi1|altsyncram:altsyncram_component
 16. Parameter Settings for User Entity Instance: control_wr_rd_for_SRAM:BLOCK4
 17. Parameter Settings for User Entity Instance: Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_0|scfifo:scfifo_component
 18. Parameter Settings for User Entity Instance: Khoi_FIFO:BLOCK_5|FIFO_Image:BLOCK_FIFO_1|scfifo:scfifo_component
 19. scfifo Parameter Settings by Entity Instance
 20. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                 ;
+------------------------------------+-----------------------------------------+
; Analysis & Synthesis Status        ; Successful - Sat May 31 20:21:14 2008   ;
; Quartus II Version                 ; 6.0 Build 178 04/27/2006 SJ Web Edition ;
; Revision Name                      ; kit_DE2                                 ;
; Top-level Entity Name              ; kit_DE2                                 ;
; Family                             ; Cyclone II                              ;
; Total logic elements               ; 614                                     ;
; Total registers                    ; 614                                     ;
; Total pins                         ; 97                                      ;
; Total virtual pins                 ; 0                                       ;
; Total memory bits                  ; 133,120                                 ;
; Embedded Multiplier 9-bit elements ; 0                                       ;
; Total PLLs                         ; 0                                       ;
+------------------------------------+-----------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP2C35F672C6       ;                    ;
; Top-level entity name                                              ; kit_DE2            ; kit_DE2            ;
; Family name                                                        ; Cyclone II         ; Stratix            ;
; Use smart compilation                                              ; Off                ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; Maximum DSP Block Usage                                            ; Unlimited          ; Unlimited          ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;