kit_de2.v

VGA sourcecodes/documents

module	kit_DE2	(	CLOCK_50,
					KEY,
					LEDR,
					SW,
					///////Giao dien VGA////////
					VGA_R,
					VGA_G,
					VGA_B,
					VGA_CLK,
					VGA_BLANK,
					VGA_SYNC,
					VGA_HS,
					VGA_VS,
					//////Giao dien UART///////
					UART_RXD,
					//UART_TXD,
					//////Giao dien SRAM///////
					SRAM_ADDR,
					SRAM_DQ,
					SRAM_WE_N,
					SRAM_OE_N,
					SRAM_UB_N,
					SRAM_LB_N,
					SRAM_CE_N
				);
	input	CLOCK_50;
	input	[1:0]KEY;
	input	[0:0]SW;
	output	[17:0]LEDR;
////////////////////////////	UART	////////////////////////////
//output			UART_TXD;				//	UART Transmitter
input			UART_RXD;				//	UART Receiver
////////////////////////	SRAM Interface	////////////////////////
inout	[15:0]	SRAM_DQ;				//	SRAM Data bus 16 Bits
output	[17:0]	SRAM_ADDR;				//	SRAM Address bus 18 Bits
output			SRAM_UB_N;				//	SRAM High-byte Data Mask
output			SRAM_LB_N;				//	SRAM Low-byte Data Mask 
output			SRAM_WE_N;				//	SRAM Write Enable
output			SRAM_CE_N;				//	SRAM Chip Enable
output			SRAM_OE_N;				//	SRAM Output Enable
////////////////////////	VGA			////////////////////////////
output			VGA_CLK;   				//	VGA Clock
output			VGA_HS;					//	VGA H_SYNC
output			VGA_VS;					//	VGA V_SYNC
output			VGA_BLANK;				//	VGA BLANK
output			VGA_SYNC;				//	VGA SYNC
output	[9:0]	VGA_R;   				//	VGA Red[9:0]
output	[9:0]	VGA_G;	 				//	VGA Green[9:0]
output	[9:0]	VGA_B;   				//	VGA Blue[9:0]

///////////////// tao clock 25Mhz/////////////////////////////////////////////////////////
reg	clock;
always	@ (posedge CLOCK_50)
	clock <= ~clock;

/////////////////////////////////////////////////////////////////////////////////////////
	wire	reset = KEY[0];
	
	wire	[7:0]RxD_data;
	wire	 RxD_data_ready;
async_receiver	BLOCK1(	.clk(clock),
						.RxD(UART_RXD),
						.RxD_data_ready(RxD_data_ready), 
						.RxD_data(RxD_data) 
					  );
					
vga_controller 	BLOCK2 (	.clock(clock),
							.reset(reset),
							///// interface VGA ///////
							.vga_clk(VGA_CLK),
							.vga_hs(VGA_HS),
							.vga_vs(VGA_VS),
							.vga_blank(VGA_BLANK),
							.vga_sync(VGA_SYNC),
							.vga_r(VGA_R),
							.vga_b(VGA_B),
							.vga_g(VGA_G),
							///// tin hieu vao ////////
							.wr_address(wr_address),
							.do_write(do_write),
							.data_colour(data_colour),
							.clear_do_read_on_SRAM(clear_do_read_on_SRAM),
							.enable_do_read_on_SRAM(enable_do_read_on_SRAM),
							///// out signal for SRAM_Controller ////////
							.wr_request(wr_request),
							.done_dislay1(done_dislay1)
					  );
	wire	wr_request;
	wire	done_dislay1;
					
SRAM_interface	BLOCK3 (	
						.in_address(in_address),
						.wr_or_rd(wr_or_rd),
						.in_data(in_data),
						//////////// interface cua SRAM ///////////////////
						.oSRAM_DQ(SRAM_DQ),
						.oSRAM_ADDR(SRAM_ADDR),
						.oSRAM_UB_N(SRAM_UB_N),
						.oSRAM_LB_N(SRAM_LB_N),
						.oSRAM_WE_N(SRAM_WE_N),
						.oSRAM_CE_N(SRAM_CE_N),
						.oSRAM_OE_N(SRAM_OE_N),
						/////////// data for ram vga //////////////////////
						.data_ram_vga(data_ram_vga)
					   );
	wire	[15:0]data_ram_vga;

control_wr_rd_for_SRAM	BLOCK4(
									.clock(clock),
									.reset(reset),
									.key(KEY[1]),
									.sw (SW[0]),
									//////////// from BLOCK processing image ////////////
									.signal_data_valid(flag_signal_data_valid),
									.data_value(out_pixel),
									//////////// from VGA ////////////
									.wr_request(wr_request),
									.done_dislay1(done_dislay1),
									//////////// signal for SRAM_Controller /////////////
									.in_address(in_address),
									.wr_or_rd(wr_or_rd),
									.in_data(in_data),
									/////////// data from SRAM //////////////////////////
									.data_Ram_vga(data_ram_vga),
									////////// signal for VGA_Controller ////////////////
									.wr_address(wr_address),
									.do_write(do_write),
									.data_colour(data_colour),
									.clear_do_read_on_SRAM(clear_do_read_on_SRAM),
									.enable_do_read_on_SRAM(enable_do_read_on_SRAM),
									.wr_address_SRAM (LEDR)
								);
	wire	[13:0]wr_address;
	wire	do_write;
	wire	[7:0]data_colour;
	wire	set_wr_request_from_SRAM;
	wire	clear_do_read_on_SRAM;
	wire	enable_do_read_on_SRAM;	
	
	wire	[17:0]in_address;
	wire	[15:0]in_data;
	wire	wr_or_rd;			

	wire	flag_RxD_data_ready;
	reg		[7:0]RxD_data_valid;
	
Khoi_phat_hien_canh_len BLOCK_DE2(clock,RxD_data_ready,flag_RxD_data_ready);
	
Khoi_FIFO 	BLOCK_5	(
					.clock(clock),
					.reset(reset),
					/////////////////////////
					.data_from_UART(RxD_data),
					.data_ready_from_UART(flag_RxD_data_ready),
					/////////////////////////
					.signal_data_valid(signal_data_valid),
					/////// 9 reg for BLOCK processing //////
					.register1(register1),
					.register2(register2),
					.register3(register3),
					.register4(register4),
					.register5(register5),
					.register6(register6),
					.register7(register7),
					.register8(register8),
					.register9(register9) 
				   );
	wire	signal_data_valid;
	wire	[7:0]register1;
	wire	[7:0]register2;
	wire	[7:0]register3;
	wire	[7:0]register4;
	wire	[7:0]register5;
	wire	[7:0]register6;
	wire	[7:0]register7;
	wire	[7:0]register8;
	wire	[7:0]register9;
				
Processing_image 	BLOCK_6(	
							.clock(clock),
							.reset(reset),
							////////////
							.signal_data_valid(signal_data_valid),
							////////////
							.register1(register1),
							.register2(register2),
							.register3(register3),
							.register4(register4),
							.register5(register5),
							.register6(register6),
							.register7(register7),
							.register8(register8),
							.register9(register9), 
							//
							.flag_signal_data_valid(flag_signal_data_valid),
							.out_pixel(out_pixel)
						  );
	wire	flag_signal_data_valid;					
	wire	[7:0]out_pixel;
											
endmodule