processing_image.v

VGA sourcecodes/documents

module	Processing_image (	clock,
							reset,
							signal_data_valid,
							register1,
							register2,
							register3,
							register4,
							register5,
							register6,
							register7,
							register8,
							register9,
							//
							flag_signal_data_valid,
							out_pixel
						  );
	input	clock;
	input 	reset;
	input	signal_data_valid;
	input	[7:0]register1;
	input	[7:0]register2;
	input	[7:0]register3;
	input	[7:0]register4;
	input	[7:0]register5;
	input	[7:0]register6;
	input	[7:0]register7;
	input	[7:0]register8;
	input	[7:0]register9;
	
	output	reg flag_signal_data_valid;
	output	[7:0]out_pixel = out[13:6];
	
	reg [13:0]out;
	
	reg		temp1,temp2,temp3,temp4,temp5;
	
always @ (posedge clock or negedge reset)						
	begin
		if (!reset)
			begin
				temp1 <= 0;
				temp2 <= 0;
				temp3 <= 0;
				temp4 <= 0;
				temp5 <= 0;
				flag_signal_data_valid <= 0;
			end
		else
			begin
				temp1 <= signal_data_valid;
				temp2 <= temp1;
				temp3 <= temp2;
				temp4 <= temp3;
				temp5 <= temp4;
				flag_signal_data_valid <= temp5;
			end
	end


/////////////////////////////////////////////////////////////////////////	
	wire	[12:0]out2 ;
	wire	[12:0]out1 ;
	
Processing_image_0 BLOCK_Processing_0(	clock,
										reset,
										register1,
										register2,
										register3,
										register4,
										register5,
										register6,
										register7,
										register8,
										register9,
										out2
									 );
									
Processing_image_1 BLOCK_Processing_1(	clock,
										reset,
										register1,
										register2,
										register3,
										register4,
										register5,
										register6,
										register7,
										register8,
										register9,
										out1
								  );									
	
	always @ (posedge clock or negedge reset)
		begin
			if (! reset)
				out <= 0;
			else
				out <= out1 + out2	;
		end		
	
endmodule