control_wr_rd_for_sram.v

VGA sourcecodes/documents

module	control_wr_rd_for_SRAM	(
									clock,
									reset,
									key,
									sw,
									//////////// from BLOCK processing image ////////////
									signal_data_valid,
									data_value,
									//////////// from VGA ////////////
									wr_request,
									done_dislay1,
									//////////// signal for SRAM_Controller /////////////
									in_address,
									wr_or_rd,
									in_data,
									/////////// data from SRAM //////////////////////////
									data_Ram_vga,
									////////// signal for VGA_Controller ////////////////
									wr_address,
									do_write,
									data_colour,
									//
									clear_do_read_on_SRAM,
									enable_do_read_on_SRAM,
									wr_address_SRAM
								);
	input	clock;
	input	reset;
	input	signal_data_valid;
	input	[7:0]data_value;
	output	[17:0]wr_address_SRAM;
	input 	key;
	input	wr_request;
	input	done_dislay1;
	input	sw;
	
	output	reg[17:0]in_address;
	output	reg wr_or_rd;
	output	reg[15:0]in_data;
	
	input	[15:0]data_Ram_vga;
	
	output	reg[13:0]wr_address;
	output	do_write;
	output	reg[7:0]data_colour;
	
	output	 clear_do_read_on_SRAM;
	output	reg enable_do_read_on_SRAM;
	
///////////////////////// State machine read or write for SRAM  ///////////////////////	
parameter	Wait_buffer_Low = 2'd0;
parameter	Buffer_data_Low_full = 2'd1; 
parameter	Wait_buffer_High = 2'd2;
parameter	Buffer_data_High_full = 2'd3;

	reg 	[1:0]current_state;
	reg		[1:0]next_state;
	
always	@ (posedge clock )
	current_state = next_state ;
	
always	@(*)
	begin
		if (! reset)
			next_state = Wait_buffer_Low;
		else
			case (current_state)
			Wait_buffer_Low:
				begin
					if(signal_data_valid)
						next_state = Buffer_data_Low_full;
					else
						next_state = Wait_buffer_Low;
				end		
 			Buffer_data_Low_full:
				begin
					next_state = Wait_buffer_High;
				end
			Wait_buffer_High:
				begin
					if(signal_data_valid)
						next_state = Buffer_data_High_full;
					else
						next_state = Wait_buffer_High;
				end		
			Buffer_data_High_full:
				begin
					next_state = Wait_buffer_Low;
				end
			default: 	next_state = Wait_buffer_Low;
			endcase
	end	
		
////////////////////////// data write in SRAM ///////////////////////////////////
	reg		[7:0]data_low;
	reg		[7:0]data_high;

always @(posedge clock or negedge reset)		
	begin
		if(!reset)
			begin
				data_low <= 0;
				data_high <= 0;
			end
		else if (current_state == Wait_buffer_Low && signal_data_valid )	
			data_low <= data_value;
		else if (current_state == Wait_buffer_High && signal_data_valid )	
			data_high <= data_value;
		else;
	end		
	
	wire	[15:0]in_data_0 = {data_high,data_low}; // sync with current_state == Buffer_data_High_full
	reg		[15:0]in_data_1;
	
always @(posedge clock)
	in_data_1 <= in_data_0;
	
	wire	[15:0]in_data_in = in_data_1;

always @(posedge clock or negedge reset)		
	begin
		if(!reset)
			in_data  <= 0;
		else
			begin
				if (flag_wr_start)
					in_data <= in_data_in;
			end
	end
	
//////////////////////////// block add for create wr_address for SRAM ///////////////////////
	wire	flag_wr_start_in = (current_state == Buffer_data_High_full) ? 1'b1 : 1'b0;
	reg		flag_wr_start;
	reg		[17:0]counter_address_wr;
	wire	[17:0]wr_address_SRAM = counter_address_wr;

///////////////////////// update flag write ///////////////////////////////////////////////
always @(posedge clock or negedge reset)		
	begin
		if(!reset)
			flag_wr_start = 0;
		else
			flag_wr_start = flag_wr_start_in;
	end	
	
/////////////////////// create write address for SRAM ////////////////////////////////////	
always @(posedge clock or negedge reset)		
	begin
		if(!reset)
			counter_address_wr  = 0;
		else
			begin
				if (flag_wr_start)
					counter_address_wr = counter_address_wr  + 18'd1;
			end
	end

//////////////////////// create signal write enable for SRAM //////////////////////////
always @(posedge clock or negedge reset)		
	begin
		if(!reset)	
			wr_or_rd = 0;
		else
			wr_or_rd = flag_wr_start;
	end
	
////////////////// create signal read SRAM & provide address & data for Ram VGA //////////////
	wire	flag_rd_start_in = ~flag_wr_start_in & wr_request;
	reg	flag_rd_start;
	reg		[18:0]counter_rd_address;	
	wire	[17:0]rd_address_SRAM = counter_rd_address[18:1];

always @(posedge clock or negedge reset)		
	begin
		if(!reset)
			flag_rd_start = 0;
		else
			flag_rd_start = flag_rd_start_in;
	end	

	wire	flag_rd_start_0,flag_rd_start_1;
	D_FFs 	C13	(clock,reset,flag_rd_start,flag_rd_start_0);
	D_FFs 	C14	(clock,reset,flag_rd_start_0,flag_rd_start_1);
	
///// wr_enable to Ram VGA	
	assign	do_write = flag_rd_start_1; 
	
///// data_wr to Ram VGA
	wire	[7:0]data_colour_in = hi_byte ? data_Ram_vga[15:8] : data_Ram_vga[7:0];
	 
always @(posedge clock or negedge reset)		
	begin
		if(!reset)
			data_colour <= 0;
		else
			data_colour <= data_colour_in;
	end			
	
///// address_wr to Ram VGA
	wire	[13:0]wr_address_in = {in_address[12:0],hi_byte};

always @(posedge clock or negedge reset)		
	begin
		if(!reset)
			wr_address <= 0 ;
		else
			begin
				if (flag_rd_start_0)	
					wr_address <= wr_address_in; 
			end
	end	

//////////////////// create read address for SRAM ////////////////////////////////////////
always @(posedge clock or negedge reset)		
	begin
		if(!reset)
			counter_rd_address <= 18'd0;
		else
			begin
				if (flag_rd_start)
					counter_rd_address <= counter_rd_address + 19'd1;
			end
	end
	
//////////////////// chose address for SRAM from read & write address //////////////////
always @(posedge clock or negedge reset)		
	begin
		if(!reset)
			in_address <= 0 ;
		else
			begin
				if (flag_wr_start)	
					in_address <= wr_address_SRAM;
				else if (flag_rd_start)
					in_address <= rd_address_SRAM;
				else;
			end
	end
	
///////////////// create signal hi_byte or lo_byte for SRAM ///////////////////////////
	wire	hi_byte_in = counter_rd_address[0];
	reg		hi_byte;
	
always @(posedge clock or negedge reset)		
	begin
		if(!reset)
			hi_byte <= 0;
		else
			hi_byte <= hi_byte_in;
	end
					
////////////////// block create signal controller write or read //////////////////////////

	wire	start_write_image = (counter_address_wr[17:13] == 31 ) ? 1'b1 : 1'b0;
	
	wire	set_start_write_image = start_write_image & done_dislay1;
	
	wire	clear_do_read_on_SRAM_in = (counter_rd_address[13:0] == 16381);	
	
	wire	hanh = sw ? (counter_rd_address[18:14] == 31) : (counter_rd_address[18:14] == 0);
		
	wire	clear_enable_do_read_on_SRAM = clear_do_read_on_SRAM_in & hanh;
	
	D_FFs 	C15	(clock,reset,clear_do_read_on_SRAM_in,clear_do_read_on_SRAM);

always @(posedge clock or negedge reset)
	begin
		if (! reset)
				enable_do_read_on_SRAM = 0;
		else
			begin
				if (set_start_write_image | set_start_write_image_0 )
					enable_do_read_on_SRAM = 1;
				else if (clear_enable_do_read_on_SRAM)
					enable_do_read_on_SRAM = 0;
				else;	
			end	
	end	
	wire	set_start_write_image_0;
	Khoi_phat_hien_canh_len BLOCK_DE(clock,key,set_start_write_image_0);

	
	
endmodule