📄 sevseg.rpt
字号:
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\zhao\vhdl\sevseg\sevseg.rpt
sevseg
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 23 OR2 ! 4 0 1 0 ~49~3
- 3 - A 23 OR2 ! 4 0 1 0 ~54~3
- 4 - A 35 OR2 4 0 1 0 ~58~2
- 7 - A 35 OR2 ! 4 0 1 0 ~64~4
- 1 - A 35 OR2 ! 4 0 1 0 ~68~2
- 2 - A 35 OR2 ! 4 0 1 0 ~72~2
- 3 - A 35 OR2 ! 4 0 1 0 ~77~3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\zhao\vhdl\sevseg\sevseg.rpt
sevseg
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/144( 2%) 0/ 72( 0%) 0/ 72( 0%) 4/16( 25%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 4/ 72( 5%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 3/ 72( 4%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\zhao\vhdl\sevseg\sevseg.rpt
sevseg
** EQUATIONS **
B0 : INPUT;
B1 : INPUT;
B2 : INPUT;
B3 : INPUT;
-- Node name is 'a'
-- Equation name is 'a', type is output
a = !~49~3;
-- Node name is 'b'
-- Equation name is 'b', type is output
b = !~54~3;
-- Node name is 'c'
-- Equation name is 'c', type is output
c = ~58~2;
-- Node name is 'd'
-- Equation name is 'd', type is output
d = !~64~4;
-- Node name is 'e'
-- Equation name is 'e', type is output
e = !~68~2;
-- Node name is 'f'
-- Equation name is 'f', type is output
f = !~72~2;
-- Node name is 'g'
-- Equation name is 'g', type is output
g = !~77~3;
-- Node name is '~49~3'
-- Equation name is '~49~3', location is LC2_A23, type is buried.
!~49~3 = ~49~3~NOT;
~49~3~NOT = LCELL( _EQ001);
_EQ001 = !B0 & !B2 & !B3
# B0 & B2 & !B3
# B1 & !B3
# !B1 & !B2 & B3;
-- Node name is '~54~3'
-- Equation name is '~54~3', location is LC3_A23, type is buried.
!~54~3 = ~54~3~NOT;
~54~3~NOT = LCELL( _EQ002);
_EQ002 = !B1 & !B2
# B0 & B1 & !B3
# !B0 & !B1 & !B3
# !B2 & !B3;
-- Node name is '~58~2'
-- Equation name is '~58~2', location is LC4_A35, type is buried.
~58~2 = LCELL( _EQ003);
_EQ003 = !B1 & !B2
# B0 & !B3
# B2 & !B3;
-- Node name is '~64~4'
-- Equation name is '~64~4', location is LC7_A35, type is buried.
!~64~4 = ~64~4~NOT;
~64~4~NOT = LCELL( _EQ004);
_EQ004 = !B0 & B1 & !B3
# !B0 & !B2 & !B3
# !B1 & !B2 & B3
# B0 & !B1 & B2 & !B3
# B1 & !B2 & !B3;
-- Node name is '~68~2'
-- Equation name is '~68~2', location is LC1_A35, type is buried.
!~68~2 = ~68~2~NOT;
~68~2~NOT = LCELL( _EQ005);
_EQ005 = !B0 & !B1 & !B2
# !B0 & B1 & !B3;
-- Node name is '~72~2'
-- Equation name is '~72~2', location is LC2_A35, type is buried.
!~72~2 = ~72~2~NOT;
~72~2~NOT = LCELL( _EQ006);
_EQ006 = !B1 & !B2 & B3
# !B0 & !B1 & !B3
# B2 & !B3;
-- Node name is '~77~3'
-- Equation name is '~77~3', location is LC3_A35, type is buried.
!~77~3 = ~77~3~NOT;
~77~3~NOT = LCELL( _EQ007);
_EQ007 = B1 & !B2 & !B3
# !B1 & !B2 & B3
# !B1 & B2 & !B3
# !B0 & B2 & !B3;
Project Information d:\zhao\vhdl\sevseg\sevseg.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 25,223K
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