sms4_cal.v

Verilog实现的SMS4

module           SMS4_Cal  (
                            clk         	,    
                            rst_n           	,
			     
			    SMS4_sw_rst		,	    
                        
			    
			    secret_reg,
			    data_reg,
                           
			   
			    SMS4_ready	,
			    SMS4_DataOut        ,
			    
			    start_pulse		,
			    logic_start    	, 
			    SMS4_encrypt_start  ,       
			    secret_update	, 
			    secret_update_clr	
                           
			    
                                  );  
				  
				                                    
                                                                                  
input clk         ;
input rst_n       ;
input SMS4_sw_rst;
input start_pulse;

input [127:0] secret_reg;
input [127:0] data_reg;

input logic_start;


	
input SMS4_encrypt_start;	
input secret_update;

output [127:0] SMS4_DataOut;
output  SMS4_ready;
output secret_update_clr;

// internal signal
reg [31:0]   data_out_reg0;
reg [31:0]   data_out_reg1;
reg [31:0]   data_out_reg2;
reg [31:0]   data_out_reg3;
wire SMS4_ready;
reg  ready_delay;                            
wire one_ring_end;
wire [31:0]  t_in ;
reg [31:0]  t_out ;
wire [31:0]  lc_out_secret; 
wire [31:0]  lc_out_data ;
wire [31:0]  lc_out ;
wire [31:0]  ring_out ;
wire [31:0] common_reg3;
wire [31:0] common_reg2;
wire [31:0] common_reg1;
wire [31:0] common_reg0;
wire [31:0] common_para;
wire secret_or_data;
wire [31:0] parameter_ck;

reg[4:0] cal_t;
reg [3:0] cnt_in_ring;
reg data_ready;
reg [31:0] ring_secret;
reg cal_secret;
reg cal_data;

wire [31:0] secret_reg3;
wire [31:0] secret_reg2;
wire [31:0] secret_reg1;
wire [31:0] secret_reg0;

wire [31:0] data_reg3;
wire [31:0] data_reg2;
wire [31:0] data_reg1;
wire [31:0] data_reg0;



// the 32 secret reg for store extend secret 
reg [31:0] secret_ext_reg0,secret_ext_reg31;
reg [31:0] secret_ext_reg1,secret_ext_reg11,secret_ext_reg21;
reg [31:0] secret_ext_reg2,secret_ext_reg12,secret_ext_reg22;
reg [31:0] secret_ext_reg3,secret_ext_reg13,secret_ext_reg23;
reg [31:0] secret_ext_reg4,secret_ext_reg14,secret_ext_reg24;
reg [31:0] secret_ext_reg5,secret_ext_reg15,secret_ext_reg25;
reg [31:0] secret_ext_reg6,secret_ext_reg16,secret_ext_reg26;
reg [31:0] secret_ext_reg7,secret_ext_reg17,secret_ext_reg27;
reg [31:0] secret_ext_reg8,secret_ext_reg18,secret_ext_reg28;
reg [31:0] secret_ext_reg9,secret_ext_reg19,secret_ext_reg29;
reg [31:0] secret_ext_reg10,secret_ext_reg20,secret_ext_reg30;

reg secret_update_clr_delay;
// the system parameter constant of 32*4 key.

parameter[31:0] fk0  =  32'ha3b1bac6;
parameter[31:0] fk1  =  32'h56aa3350;
parameter[31:0] fk2  =  32'h677d9197;
parameter[31:0] fk3  =  32'hb27022dc;



assign secret_reg3 = secret_reg[127:96];
assign secret_reg2 = secret_reg[95:64];
assign secret_reg1 = secret_reg[63:32];
assign secret_reg0 = secret_reg[31:0];

assign data_reg3 = data_reg[127:96];
assign data_reg2 = data_reg[95:64];
assign data_reg1 = data_reg[63:32];
assign data_reg0 = data_reg[31:0];


// encrypt and decrypt the data 
assign secret_or_data = cal_secret;	// 1: secret cal period,0:data cal period
assign parameter_ck = ck(cal_t);

assign common_reg3 = data_out_reg3;
assign common_reg2 = data_out_reg2;
assign common_reg1 = data_out_reg1;
assign common_reg0 = data_out_reg0;
assign common_para = secret_or_data ? parameter_ck : ring_secret;

// secret_ring = T(secret1,secret2,secret3,parameter_ck);
// t_in: the input of function litter t
// t_out : the output of function litter t
// lc_out : the output of function linechange
// secret_ring : the Ki+4 , the ring secret

assign t_in = common_reg3 ^ common_reg2 ^ common_reg1 ^ common_para;
reg [7:0] t_out_3;
reg [7:0] t_out_2;
reg [7:0] t_out_1;
reg [7:0] t_out_0;
always@(posedge clk or negedge rst_n)
begin
  if(!rst_n)
  begin
    t_out_3 <= 8'h00;
    t_out_2 <= 8'h00;
    t_out_1 <= 8'h00;
    t_out_0 <= 8'h00;
    t_out   <= 32'h0000;
  end
  else if(SMS4_sw_rst)
  begin
    t_out_3 <= 8'h00;
    t_out_2 <= 8'h00;
    t_out_1 <= 8'h00;
    t_out_0 <= 8'h00;
    t_out   <= 32'h0000;
  end
  else if(logic_start && cnt_in_ring==4'd0)
    t_out_3 <= sbox(t_in[31:24]);
  else if(logic_start && cnt_in_ring==4'd1)
    t_out_2 <= sbox(t_in[23:16]);
  else if(logic_start && cnt_in_ring==4'd2)
    t_out_1 <= sbox(t_in[15:8]);
  else if(logic_start && cnt_in_ring==4'd3)
    t_out_0 <= sbox(t_in[7:0]);
  else if(logic_start && cnt_in_ring==4'd4)
    t_out <= {t_out_3,t_out_2,t_out_1,t_out_0};
end

assign lc_out_secret = lc_secret(t_out);
assign lc_out_data = lc_data(t_out);
assign lc_out = secret_or_data ? lc_out_secret : lc_out_data;
assign ring_out = common_reg0 ^ lc_out;

// cal the extend secret and store in the reg secret_ext_reg0~secret_ext_reg31

always@(posedge clk or negedge rst_n)
begin
  if(!rst_n)
  begin
	secret_ext_reg0 <= 32'd0;
	secret_ext_reg1 <= 32'd0;
	secret_ext_reg2 <= 32'd0;
	secret_ext_reg3 <= 32'd0;
	secret_ext_reg4 <= 32'd0;
	secret_ext_reg5 <= 32'd0;
	secret_ext_reg6 <= 32'd0;
	secret_ext_reg7 <= 32'd0;
	secret_ext_reg8 <= 32'd0;
	secret_ext_reg9 <= 32'd0;
	secret_ext_reg10 <= 32'd0;
	secret_ext_reg11 <= 32'd0;
	secret_ext_reg12 <= 32'd0;
	secret_ext_reg13 <= 32'd0;
	secret_ext_reg14 <= 32'd0;
	secret_ext_reg15 <= 32'd0;
	secret_ext_reg16 <= 32'd0;
	secret_ext_reg17 <= 32'd0;
	secret_ext_reg18 <= 32'd0;
	secret_ext_reg19 <= 32'd0;
	secret_ext_reg20 <= 32'd0;
	secret_ext_reg21 <= 32'd0;
	secret_ext_reg22 <= 32'd0;
	secret_ext_reg23 <= 32'd0;
	secret_ext_reg24 <= 32'd0;
	secret_ext_reg25 <= 32'd0;
	secret_ext_reg26 <= 32'd0;
	secret_ext_reg27 <= 32'd0;
	secret_ext_reg28 <= 32'd0;
	secret_ext_reg29 <= 32'd0;
	secret_ext_reg30 <= 32'd0;
	secret_ext_reg31 <= 32'd0;
  end
  else if(cal_secret && cnt_in_ring==4'd5)
  begin
	    case(cal_t)
	    5'd0:secret_ext_reg0 <= ring_out; 
	    5'd1:secret_ext_reg1 <= ring_out; 
	    5'd2:secret_ext_reg2 <= ring_out; 
	    5'd3:secret_ext_reg3 <= ring_out; 
	    5'd4:secret_ext_reg4 <= ring_out; 
	    5'd5:secret_ext_reg5 <= ring_out; 
	    5'd6:secret_ext_reg6 <= ring_out; 
	    5'd7:secret_ext_reg7 <= ring_out; 
	    5'd8:secret_ext_reg8 <= ring_out; 
	    5'd9:secret_ext_reg9 <= ring_out; 
	    5'd10:secret_ext_reg10 <= ring_out; 
	    5'd11:secret_ext_reg11 <= ring_out; 
	    5'd12:secret_ext_reg12 <= ring_out; 
	    5'd13:secret_ext_reg13 <= ring_out; 
	    5'd14:secret_ext_reg14 <= ring_out; 
	    5'd15:secret_ext_reg15 <= ring_out; 
	    5'd16:secret_ext_reg16 <= ring_out; 
	    5'd17:secret_ext_reg17 <= ring_out; 
	    5'd18:secret_ext_reg18 <= ring_out; 
	    5'd19:secret_ext_reg19 <= ring_out; 
	    5'd20:secret_ext_reg20 <= ring_out; 
	    5'd21:secret_ext_reg21 <= ring_out; 
 	    5'd22:secret_ext_reg22 <= ring_out; 
 	    5'd23:secret_ext_reg23 <= ring_out; 
	    5'd24:secret_ext_reg24 <= ring_out; 
	    5'd25:secret_ext_reg25 <= ring_out; 
	    5'd26:secret_ext_reg26 <= ring_out; 
	    5'd27:secret_ext_reg27 <= ring_out; 
	    5'd28:secret_ext_reg28 <= ring_out; 
	    5'd29:secret_ext_reg29 <= ring_out; 
	    5'd30:secret_ext_reg30 <= ring_out; 
	    5'd31:secret_ext_reg31 <= ring_out; 
            endcase
  end
end

// gen the ring secret ,the four reg 


assign SMS4_DataOut = {data_out_reg3,data_out_reg2,data_out_reg1,data_out_reg0};
always@(posedge clk or negedge rst_n)
begin
  if(!rst_n)
  begin
    data_out_reg0 <= 32'h0000;
    data_out_reg1 <= 32'h0000;
    data_out_reg2 <= 32'h0000;
    data_out_reg3 <= 32'h0000;
  end
  else if(SMS4_sw_rst)
  begin
    data_out_reg0 <= 32'h0000;
    data_out_reg1 <= 32'h0000;
    data_out_reg2 <= 32'h0000;
    data_out_reg3 <= 32'h0000;
  end
  else if(start_pulse && secret_update)	// add init ring key value at calculation ring key
  begin
    data_out_reg0 <= fk0^secret_reg3;
    data_out_reg1 <= fk1^secret_reg2;
    data_out_reg2 <= fk2^secret_reg1;
    data_out_reg3 <= fk3^secret_reg0;
  end
// load data at encry or decry the data, one case is input key , one case is no input key
  else if((start_pulse && !secret_update) || (secret_update && secret_update_clr))	
  begin
    data_out_reg0 <= data_reg3;
    data_out_reg1 <= data_reg2;
    data_out_reg2 <= data_reg1;
    data_out_reg3 <= data_reg0;
  end
// control loop of four register, one for control calculation ring secret and one for calculation data 
  else if((cal_secret && cnt_in_ring == 4'd5) || (cal_data && one_ring_end))
  begin 
    data_out_reg0 <= data_out_reg1;
    data_out_reg1 <= data_out_reg2;
    data_out_reg2 <= data_out_reg3;
    data_out_reg3 <= ring_out;
  end
end

always@(SMS4_encrypt_start or cal_t or secret_ext_reg0 or secret_ext_reg1 or secret_ext_reg2 or secret_ext_reg3 
		or secret_ext_reg4 or secret_ext_reg5 or secret_ext_reg6 or secret_ext_reg7    	
		or secret_ext_reg8 or secret_ext_reg9 or secret_ext_reg10 or secret_ext_reg11 
		or secret_ext_reg12 or secret_ext_reg13 or secret_ext_reg14 or secret_ext_reg15 
		or secret_ext_reg16 or secret_ext_reg17 or secret_ext_reg18 or secret_ext_reg19 
		or secret_ext_reg20 or secret_ext_reg21 or secret_ext_reg22 or secret_ext_reg23 
		or secret_ext_reg24 or secret_ext_reg25 or secret_ext_reg26 or secret_ext_reg27 
		or secret_ext_reg28 or secret_ext_reg29 or secret_ext_reg30 or secret_ext_reg31) 
begin
  if(SMS4_encrypt_start)
  begin
    case(cal_t)
    5'd0: ring_secret <= secret_ext_reg0;
    5'd1: ring_secret <= secret_ext_reg1;
    5'd2: ring_secret <= secret_ext_reg2;
    5'd3: ring_secret <= secret_ext_reg3;
    5'd4: ring_secret <= secret_ext_reg4;
    5'd5: ring_secret <= secret_ext_reg5;
    5'd6: ring_secret <= secret_ext_reg6;
    5'd7: ring_secret <= secret_ext_reg7;
    5'd8: ring_secret <= secret_ext_reg8;
    5'd9: ring_secret <= secret_ext_reg9;
    5'd10: ring_secret <= secret_ext_reg10;
    5'd11: ring_secret <= secret_ext_reg11;
    5'd12: ring_secret <= secret_ext_reg12;
    5'd13: ring_secret <= secret_ext_reg13;
    5'd14: ring_secret <= secret_ext_reg14;
    5'd15: ring_secret <= secret_ext_reg15;
    5'd16: ring_secret <= secret_ext_reg16;
    5'd17: ring_secret <= secret_ext_reg17;
    5'd18: ring_secret <= secret_ext_reg18;
    5'd19: ring_secret <= secret_ext_reg19;
    5'd20: ring_secret <= secret_ext_reg20;
    5'd21: ring_secret <= secret_ext_reg21;
    5'd22: ring_secret <= secret_ext_reg22;
    5'd23: ring_secret <= secret_ext_reg23;
    5'd24: ring_secret <= secret_ext_reg24;
    5'd25: ring_secret <= secret_ext_reg25;
    5'd26: ring_secret <= secret_ext_reg26;
    5'd27: ring_secret <= secret_ext_reg27;
    5'd28: ring_secret <= secret_ext_reg28;
    5'd29: ring_secret <= secret_ext_reg29;
    5'd30: ring_secret <= secret_ext_reg30;
    5'd31: ring_secret <= secret_ext_reg31;
    endcase
  end
  else 
  begin
    case(cal_t)
    5'd0: ring_secret <= secret_ext_reg31;
    5'd1: ring_secret <= secret_ext_reg30;
    5'd2: ring_secret <= secret_ext_reg29;
    5'd3: ring_secret <= secret_ext_reg28;
    5'd4: ring_secret <= secret_ext_reg27;
    5'd5: ring_secret <= secret_ext_reg26;
    5'd6: ring_secret <= secret_ext_reg25;
    5'd7: ring_secret <= secret_ext_reg24;
    5'd8: ring_secret <= secret_ext_reg23;
    5'd9: ring_secret <= secret_ext_reg22;
    5'd10: ring_secret <= secret_ext_reg21;
    5'd11: ring_secret <= secret_ext_reg20;
    5'd12: ring_secret <= secret_ext_reg19;
    5'd13: ring_secret <= secret_ext_reg18;
    5'd14: ring_secret <= secret_ext_reg17;
    5'd15: ring_secret <= secret_ext_reg16;
    5'd16: ring_secret <= secret_ext_reg15;
    5'd17: ring_secret <= secret_ext_reg14;
    5'd18: ring_secret <= secret_ext_reg13;
    5'd19: ring_secret <= secret_ext_reg12;
    5'd20: ring_secret <= secret_ext_reg11;
    5'd21: ring_secret <= secret_ext_reg10;
    5'd22: ring_secret <= secret_ext_reg9;
    5'd23: ring_secret <= secret_ext_reg8;
    5'd24: ring_secret <= secret_ext_reg7;
    5'd25: ring_secret <= secret_ext_reg6;
    5'd26: ring_secret <= secret_ext_reg5;
    5'd27: ring_secret <= secret_ext_reg4;
    5'd28: ring_secret <= secret_ext_reg3;
    5'd29: ring_secret <= secret_ext_reg2;
    5'd30: ring_secret <= secret_ext_reg1;
    5'd31: ring_secret <= secret_ext_reg0;
    endcase
  end
end

// cnt for count in a ring of encrypt calculation
always@(posedge clk or negedge rst_n)
begin
  if(!rst_n)
    cnt_in_ring <= 4'd0;
  else if(SMS4_sw_rst || one_ring_end || SMS4_ready)
    cnt_in_ring <= 4'd0;
  else if(secret_update_clr_delay)
    cnt_in_ring <= 4'd0;
  else if(cal_data || cal_secret) 
    cnt_in_ring <= cnt_in_ring + 1'b1;
end

// one ring use 7 clk
assign one_ring_end = (cnt_in_ring==4'd6);

// control counter , use to counter 32 ring encrypt calculation

always@(posedge clk or negedge rst_n)