sms4_dataio.v

Verilog实现的SMS4

module     SMS4_DataIO        (	

			 clk  ,    
                         rst_n,    
                       
		         SMS4_sw_rst,
		   
		         SMS4_DataIn,
		         
		         SMS4_load_key,
		         SMS4_load_data,
		                
		   
		         SMS4_encrypt_start,
		         SMS4_decrypt_start,   
		         
		       
		       
			SMS4_ready,	// sms4 operation over 
			
			
			
		
			secret_reg,
			data_reg,
			
			secret_update_clr,	// clear secret_udpate signal
// output
                      
			secret_update,
			

			
			start_pulse,
                        logic_start     
			
			//indicator	
                            	
					); 


input               clk;
input               rst_n;     

input          SMS4_sw_rst;

input  [31:0 ] SMS4_DataIn;

input          SMS4_load_key;
input          SMS4_load_data;


input          SMS4_encrypt_start;
input          SMS4_decrypt_start;






input  SMS4_ready;
input secret_update_clr;





output start_pulse;
output logic_start;
//output indicator;	
output secret_update;

wire start_pulse;
reg logic_start;
//wire indicator;
reg secret_update;

output [127:0] secret_reg;
output [127:0] data_reg;






reg [127:0] data_reg;
reg [127:0] secret_reg;

reg start_delay;


//assign indicator = SMS4_decrypt_start;
assign start_pulse = (SMS4_encrypt_start|SMS4_decrypt_start)&~start_delay;


always @ (posedge clk or negedge rst_n )
begin
   if(!rst_n)
      start_delay <= 1'b0;
   else if(SMS4_sw_rst) start_delay <= 1'b0;
   else  start_delay <= SMS4_encrypt_start|SMS4_decrypt_start;
end


always @ (posedge clk or negedge rst_n)begin
  if(!rst_n)  logic_start <= 1'b0;
  else if(SMS4_sw_rst) logic_start <= 1'b0;
  else if(start_pulse)   logic_start <= 1'b1;
  else if(SMS4_ready)     logic_start  <= 1'b0;
end

always @ (posedge clk or negedge rst_n )begin
  if(!rst_n)
    secret_update <= 1'b0;
  else if(secret_update_clr)
    secret_update <= 1'b0;
  else if(SMS4_load_key)
    secret_update <= 1'b1;
end



                                                                                                 
always @ (posedge clk or negedge rst_n)
begin
   if(!rst_n) 
      secret_reg <= 128'd0;
   else if(SMS4_sw_rst) secret_reg <= 128'd0;
    else begin
      if(SMS4_load_key)begin
         //if(left_first)  secret_reg <= {secret_reg[95:0],SMS4_DataIn};
	  secret_reg <= {SMS4_DataIn,secret_reg[127:32]};
      end
    end
end


always @ (posedge clk or negedge rst_n)
begin
   if(!rst_n) 
      data_reg <= 128'd0;
   else if(SMS4_sw_rst) data_reg <= 128'd0;
    else begin
      if(SMS4_load_data)begin
         //if(left_first)  data_reg <= {data_reg[95:0],SMS4_DataIn};
	  data_reg <= {SMS4_DataIn,data_reg[127:32]};
      end
    end
end


endmodule