lcd12864.fit.rpt

FPGA驱动LCD12864显示

; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers                                              ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                  ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                        ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
; Maximum number of global clocks allowed                            ; -1                             ; -1                             ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Fitter Partition Preservation Settings                                                                 ;
+------+-------------------+---------+------------------------------+------------------------+-----------+
; Name ; # Preserved Nodes ; # Nodes ; Preservation Level Requested ; Netlist Type Used      ; Hierarchy ;
+------+-------------------+---------+------------------------------+------------------------+-----------+
; Top  ; 0                 ; 144     ; Placement and Routing        ; Post-Synthesis Netlist ;           ;
+------+-------------------+---------+------------------------------+------------------------+-----------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in F:/Q80/temp/verilog/EP2C5-V5/LCD12864_v/LCD12864.pin.


+-------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                           ;
+---------------------------------------------+---------------------------+
; Resource                                    ; Usage                     ;
+---------------------------------------------+---------------------------+
; Total logic elements                        ; 78 / 4,608 ( 2 % )        ;
;     -- Combinational with no register       ; 37                        ;
;     -- Register only                        ; 0                         ;
;     -- Combinational with a register        ; 41                        ;
;                                             ;                           ;
; Logic element usage by number of LUT inputs ;                           ;
;     -- 4 input functions                    ; 30                        ;
;     -- 3 input functions                    ; 8                         ;
;     -- <=2 input functions                  ; 40                        ;
;     -- Register only                        ; 0                         ;
;                                             ;                           ;
; Logic elements by mode                      ;                           ;
;     -- normal mode                          ; 48                        ;
;     -- arithmetic mode                      ; 30                        ;
;                                             ;                           ;
; Total registers*                            ; 41 / 5,010 ( < 1 % )      ;
;     -- Dedicated logic registers            ; 41 / 4,608 ( < 1 % )      ;
;     -- I/O registers                        ; 0 / 402 ( 0 % )           ;
;                                             ;                           ;
; Total LABs:  partially or completely used   ; 5 / 288 ( 2 % )           ;
; User inserted logic elements                ; 0                         ;
; Virtual pins                                ; 0                         ;
; I/O pins                                    ; 17 / 142 ( 12 % )         ;
;     -- Clock pins                           ; 1 / 4 ( 25 % )            ;
; Global signals                              ; 1                         ;
; M4Ks                                        ; 4 / 26 ( 15 % )           ;
; Total memory bits                           ; 16,384 / 119,808 ( 14 % ) ;
; Total RAM block bits                        ; 18,432 / 119,808 ( 15 % ) ;
; Embedded Multiplier 9-bit elements          ; 0 / 26 ( 0 % )            ;
; PLLs                                        ; 0 / 2 ( 0 % )             ;
; Global clocks                               ; 1 / 8 ( 13 % )            ;
; JTAGs                                       ; 0 / 1 ( 0 % )             ;
; Average interconnect usage (total/H/V)      ; 1% / 0% / 1%              ;
; Peak interconnect usage (total/H/V)         ; 1% / 1% / 1%              ;
; Maximum fan-out node                        ; clk~clkctrl               ;
; Maximum fan-out                             ; 45                        ;
; Highest non-global fan-out signal           ; reset                     ;
; Highest non-global fan-out                  ; 31                        ;
; Total fan-out                               ; 423                       ;
; Average fan-out                             ; 2.96                      ;
+---------------------------------------------+---------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                  ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name  ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clk   ; 23    ; 1        ; 0            ; 6            ; 0           ; 1                     ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;