lcd_1602.hier_info

基于FPGA的LCD1602显示

|lcd_1602
lcd1602_e <= lcd:inst.lcd_e
clk => lcd:inst.clk
reset => lcd:inst.rst
FLASH_CE <= <VCC>
rtl8019_cs <= <VCC>
FLASH_ADDR0 <= lcd:inst.lcd_rw
FLASH_ADDR1 <= lcd:inst.lcd_rs
FLASH_DQ[0] <= lcd:inst.data[0]
FLASH_DQ[1] <= lcd:inst.data[1]
FLASH_DQ[2] <= lcd:inst.data[2]
FLASH_DQ[3] <= lcd:inst.data[3]
FLASH_DQ[4] <= lcd:inst.data[4]
FLASH_DQ[5] <= lcd:inst.data[5]
FLASH_DQ[6] <= lcd:inst.data[6]
FLASH_DQ[7] <= lcd:inst.data[7]


|lcd_1602|lcd:inst
clk => div_reg[20].CLK
clk => div_reg[19].CLK
clk => div_reg[18].CLK
clk => div_reg[17].CLK
clk => div_reg[16].CLK
clk => div_reg[15].CLK
clk => div_reg[14].CLK
clk => div_reg[13].CLK
clk => div_reg[12].CLK
clk => div_reg[11].CLK
clk => div_reg[10].CLK
clk => div_reg[9].CLK
clk => div_reg[8].CLK
clk => div_reg[7].CLK
clk => div_reg[6].CLK
clk => div_reg[5].CLK
clk => div_reg[4].CLK
clk => div_reg[3].CLK
clk => div_reg[2].CLK
clk => div_reg[1].CLK
clk => div_reg[0].CLK
clk => clk_int_r.CLK
clk => clk_int.CLK
rst => clk_int.ACLR
rst => div_reg[20].ACLR
rst => div_reg[19].ACLR
rst => div_reg[18].ACLR
rst => div_reg[17].ACLR
rst => div_reg[16].ACLR
rst => div_reg[15].ACLR
rst => div_reg[14].ACLR
rst => div_reg[13].ACLR
rst => div_reg[12].ACLR
rst => div_reg[11].ACLR
rst => div_reg[10].ACLR
rst => div_reg[9].ACLR
rst => div_reg[8].ACLR
rst => div_reg[7].ACLR
rst => div_reg[6].ACLR
rst => div_reg[5].ACLR
rst => div_reg[4].ACLR
rst => div_reg[3].ACLR
rst => div_reg[2].ACLR
rst => div_reg[1].ACLR
rst => div_reg[0].ACLR
rst => clk_int_r.ACLR
rst => data[0]~reg0.ENA
rst => lcd_rs~reg0.ENA
rst => lcd_rw~reg0.ENA
rst => data[7]~reg0.ENA
rst => data[6]~reg0.ENA
rst => data[5]~reg0.ENA
rst => data[4]~reg0.ENA
rst => data[3]~reg0.ENA
rst => data[2]~reg0.ENA
rst => data[1]~reg0.ENA
lcd_e <= clk_int.DB_MAX_OUTPUT_PORT_TYPE
lcd_rw <= lcd_rw~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_rs <= lcd_rs~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[0] <= data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[1] <= data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[2] <= data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[3] <= data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[4] <= data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[5] <= data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[6] <= data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[7] <= data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|lcd_1602|lcd:inst|char_ram:charram
address[0] => Mux6.IN69
address[0] => Mux5.IN69
address[0] => Mux4.IN69
address[0] => Mux3.IN69
address[0] => Mux2.IN69
address[0] => Mux1.IN69
address[0] => Mux0.IN69
address[1] => Mux6.IN68
address[1] => Mux5.IN68
address[1] => Mux4.IN68
address[1] => Mux3.IN68
address[1] => Mux2.IN68
address[1] => Mux1.IN68
address[1] => Mux0.IN68
address[2] => Mux6.IN67
address[2] => Mux5.IN67
address[2] => Mux4.IN67
address[2] => Mux3.IN67
address[2] => Mux2.IN67
address[2] => Mux1.IN67
address[2] => Mux0.IN67
address[3] => Mux6.IN66
address[3] => Mux5.IN66
address[3] => Mux4.IN66
address[3] => Mux3.IN66
address[3] => Mux2.IN66
address[3] => Mux1.IN66
address[3] => Mux0.IN66
address[4] => Mux6.IN65
address[4] => Mux5.IN65
address[4] => Mux4.IN65
address[4] => Mux3.IN65
address[4] => Mux2.IN65
address[4] => Mux1.IN65
address[4] => Mux0.IN65
address[5] => Mux6.IN64
address[5] => Mux5.IN64
address[5] => Mux4.IN64
address[5] => Mux3.IN64
address[5] => Mux2.IN64
address[5] => Mux1.IN64
address[5] => Mux0.IN64
data[0] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
data[1] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
data[2] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
data[3] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
data[4] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
data[5] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
data[6] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
data[7] <= <GND>