lcd_1602.tan.rpt

基于FPGA的LCD1602显示

; N/A                                     ; 264.69 MHz ( period = 3.778 ns )                    ; lcd:inst|div_reg[19] ; lcd:inst|div_reg[2]  ; clk        ; clk      ; None                        ; None                      ; 3.511 ns                ;
; N/A                                     ; 264.69 MHz ( period = 3.778 ns )                    ; lcd:inst|div_reg[19] ; lcd:inst|div_reg[1]  ; clk        ; clk      ; None                        ; None                      ; 3.511 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                      ;                      ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+----------------------+----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------------+
; tco                                                                           ;
+-------+--------------+------------+------------------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From             ; To        ; From Clock ;
+-------+--------------+------------+------------------+-----------+------------+
; N/A   ; None         ; 9.593 ns   ; lcd:inst|clk_int ; lcd1602_e ; clk        ;
+-------+--------------+------------+------------------+-----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sat Jan 10 16:27:28 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off lcd_1602 -c lcd_1602 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 210.39 MHz between source register "lcd:inst|div_reg[12]" and destination register "lcd:inst|div_reg[15]" (period= 4.753 ns)
    Info: + Longest register to register delay is 4.489 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y2_N5; Fanout = 3; REG Node = 'lcd:inst|div_reg[12]'
        Info: 2: + IC(1.140 ns) + CELL(0.370 ns) = 1.510 ns; Loc. = LCCOMB_X2_Y3_N4; Fanout = 1; COMB Node = 'lcd:inst|LessThan0~339'
        Info: 3: + IC(0.374 ns) + CELL(0.370 ns) = 2.254 ns; Loc. = LCCOMB_X2_Y3_N2; Fanout = 1; COMB Node = 'lcd:inst|LessThan0~341'
        Info: 4: + IC(0.362 ns) + CELL(0.206 ns) = 2.822 ns; Loc. = LCCOMB_X2_Y3_N0; Fanout = 22; COMB Node = 'lcd:inst|LessThan0~343'
        Info: 5: + IC(1.007 ns) + CELL(0.660 ns) = 4.489 ns; Loc. = LCFF_X2_Y2_N11; Fanout = 3; REG Node = 'lcd:inst|div_reg[15]'
        Info: Total cell delay = 1.606 ns ( 35.78 % )
        Info: Total interconnect delay = 2.883 ns ( 64.22 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.782 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 23; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.833 ns) + CELL(0.666 ns) = 2.782 ns; Loc. = LCFF_X2_Y2_N11; Fanout = 3; REG Node = 'lcd:inst|div_reg[15]'
            Info: Total cell delay = 1.806 ns ( 64.92 % )
            Info: Total interconnect delay = 0.976 ns ( 35.08 % )
        Info: - Longest clock path from clock "clk" to source register is 2.782 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 23; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.833 ns) + CELL(0.666 ns) = 2.782 ns; Loc. = LCFF_X2_Y2_N5; Fanout = 3; REG Node = 'lcd:inst|div_reg[12]'
            Info: Total cell delay = 1.806 ns ( 64.92 % )
            Info: Total interconnect delay = 0.976 ns ( 35.08 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tco from clock "clk" to destination pin "lcd1602_e" through register "lcd:inst|clk_int" is 9.593 ns
    Info: + Longest clock path from clock "clk" to source register is 2.782 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 23; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.833 ns) + CELL(0.666 ns) = 2.782 ns; Loc. = LCFF_X2_Y2_N29; Fanout = 1; REG Node = 'lcd:inst|clk_int'
        Info: Total cell delay = 1.806 ns ( 64.92 % )
        Info: Total interconnect delay = 0.976 ns ( 35.08 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 6.507 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X2_Y2_N29; Fanout = 1; REG Node = 'lcd:inst|clk_int'
        Info: 2: + IC(3.211 ns) + CELL(3.296 ns) = 6.507 ns; Loc. = PIN_163; Fanout = 0; PIN Node = 'lcd1602_e'
        Info: Total cell delay = 3.296 ns ( 50.65 % )
        Info: Total interconnect delay = 3.211 ns ( 49.35 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 114 megabytes of memory during processing
    Info: Processing ended: Sat Jan 10 16:27:29 2009
    Info: Elapsed time: 00:00:01