fpq.vhd

ISP实验分频器源程序

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:55:07 03/08/2009 
-- Design Name: 
-- Module Name:    fpq - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fpq is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC; 
           clk_1MHz : out  STD_LOGIC;
           clk_1KHz : out  STD_LOGIC;
           clk_1Hz : out  STD_LOGIC);
end fpq;

architecture Behavioral of fpq is 
 signal count_MHz:std_logic_vector(7 downto 0);
 signal count_KHz:std_logic_vector(17 downto 0);
 signal count_Hz:std_logic_vector(26 downto 0);
 signal MHz,KHz,Hz:std_logic;
begin
gen_MHz:process (clk,reset) is
begin
if reset='0' then
MHz<='0';count_MHz<=(others=>'0');
elsif rising_edge(clk) then
count_MHz<=count_MHz+'1';
if count_MHz>=40 then
count_MHz<=(others=>'0');
end if;
if count_MHz>=20 then
 MHz<='1';
 else
 MHz<='0';
 end if;
 end if;
 end process gen_MHz;
 clk_1MHz<=MHz;
 
 gen_KHz:process (clk,reset) is
begin
if reset='0' then
KHz<='0';count_KHz<=(others=>'0');
elsif rising_edge(clk) then
count_KHz<=count_KHz+'1';
if count_KHz>=40000 then
count_KHz<=(others=>'0');
end if;
if count_KHz>=20000 then
 KHz<='1';
 else
KHz<='0';
 end if;
 end if;
 end process gen_KHz;
 clk_1KHz<=KHz;
 
gen_Hz:process (clk,reset) is
begin
if reset='0' then
Hz<='0';count_Hz<=(others=>'0');
elsif rising_edge(clk) then
count_Hz<=count_Hz+'1';
if count_Hz>=40000000 then
count_Hz<=(others=>'0');
end if;
if count_Hz>=20000000 then
 Hz<='1';
 else
Hz<='0';
 end if;
 end if;
 end process gen_Hz;
clk_1Hz<=Hz;

end Behavioral;