dff asynchronous.txt

this is ram both asynchronous and synchronous reset signals which is basic for any registers and bas

---------------------------d ff asynchrnous-----------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
    Port ( reset_l : in std_logic;
           clk : in std_logic;
           data : in std_logic;
           clr_l : in std_logic;
           Q : out std_logic;
           Q_l : out std_logic);
end dff;

architecture Behavioral of dff is

begin
  process (clk,reset_l,clr_l,data)
  begin
	if (reset_l ='0') 
	then q<='1';q_l<='0';
   elsif (clr_l ='0')
	then q<='0'; q_l<='1';
	elsif (clk'event and clk='1')
	then  q<= data; q_l <=not data;
	end if ;
	 end process;
	 end behavioral; 


----------------------------test bench-----------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY dff_tb_vhd IS
END dff_tb_vhd;

ARCHITECTURE behavior OF dff_tb_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT dff
	PORT(
		reset_l : IN std_logic;
		clk : IN std_logic;
		data : IN std_logic;
		clr_l : IN std_logic;          
		Q : OUT std_logic;
		Q_l : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL reset_l :  std_logic := '0';
	SIGNAL clk :  std_logic := '0';
	SIGNAL data :  std_logic := '0';
	SIGNAL clr_l :  std_logic := '0';

	--Outputs
	SIGNAL Q :  std_logic;
	SIGNAL Q_l :  std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: dff PORT MAP(
		reset_l => reset_l,
		clk => clk,
		data => data,
		clr_l => clr_l,
		Q => Q,
		Q_l => Q_l
	);
	process (clk)
	begin
	         clk<= not clk after 5 ns;
	end process;

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		reset_l<= '0' ; wait for 10 ns;
		reset_l<='1'; 	clr_l<='1';
		data<='1'; wait for 20 ns;
		data<='0' ; wait for 5 ns;
		data<='1'; wait for 15 ns;
		clr_l<='0'; wait for 10 ns;
		clr_l<='1';
		data<='1'; wait for 20 ns;
		reset_l<='0'; wait for 10 ns;
		data<='1'; wait for 10 ns;
		reset_l<='1';
		wait; -- will wait forever
	END PROCESS;

END;