📄 test.map.rpt
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; PORT_SCANDATA ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANDATAOUT ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANDONE ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ACTIVECLOCK ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKLOSS ; PORT_CONNECTIVITY ; Untyped ;
; PORT_INCLK1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_INCLK0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_FBIN ; PORT_CONNECTIVITY ; Untyped ;
; PORT_PLLENA ; PORT_CONNECTIVITY ; Untyped ;
; PORT_CLKSWITCH ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ARESET ; PORT_CONNECTIVITY ; Untyped ;
; PORT_PFDENA ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANCLK ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANACLR ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANREAD ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCANWRITE ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
; M_TEST_SOURCE ; 5 ; Untyped ;
; C0_TEST_SOURCE ; 5 ; Untyped ;
; C1_TEST_SOURCE ; 5 ; Untyped ;
; C2_TEST_SOURCE ; 5 ; Untyped ;
; C3_TEST_SOURCE ; 5 ; Untyped ;
; C4_TEST_SOURCE ; 5 ; Untyped ;
; C5_TEST_SOURCE ; 5 ; Untyped ;
; DEVICE_FAMILY ; Stratix ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+-------------------------------+-------------------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: rs422:inst|altsyncram:reduce_nor_rtl_0 ;
+------------------------------------+----------------+-----------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------+-----------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 3 ; Untyped ;
; WIDTHAD_A ; 8 ; Untyped ;
; NUMWORDS_A ; 256 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; test0.rtl.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Stratix ; Untyped ;
; CBXI_PARAMETER ; altsyncram_h0j ; Untyped ;
+------------------------------------+----------------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/test.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Wed Aug 09 16:09:29 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test -c test
Warning: Can't analyze file -- file C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/test.vhd is missing
Info: Found 1 design units, including 1 entities, in source file test.bdf
Info: Found entity 1: test
Info: Elaborating entity "test" for the top level hierarchy
Warning: Pin "tapg1p[1..0]" is missing source
Info: Using design file rs422.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: rs422-rtl
Info: Found entity 1: rs422
Info: Elaborating entity "rs422" for hierarchy "rs422:inst"
Info: (10035) Verilog HDL or VHDL information at rs422.vhd(56): object "count1_3" declared but not used
Info: (10035) Verilog HDL or VHDL information at rs422.vhd(61): object "RAM2" declared but not used
Info: Using design file clk.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: clk-rtl
Info: Found entity 1: clk
Info: Elaborating entity "clk" for hierarchy "clk:inst12"
Info: (10035) Verilog HDL or VHDL information at clk.vhd(22): object "clk_16m" declared but not used
Info: (10035) Verilog HDL or VHDL information at clk.vhd(22): object "clk_8m" declared but not used
Info: Using design file PLL24M.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: PLL24M-SYN
Info: Found entity 1: PLL24M
Info: Elaborating entity "PLL24M" for hierarchy "PLL24M:inst7"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altpll.tdf
Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "PLL24M:inst7|altpll:altpll_component"
Info: Power-up level of register "rs422:inst|tag1" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "rs422:inst|tag1" with stuck data_in port to stuck value VCC
Info: Duplicate registers merged to single register
Info: Duplicate register "rs422:inst|p5~2" merged to single register "rs422:inst|p5~0"
Info: Duplicate register "rs422:inst|p5~4" merged to single register "rs422:inst|p5~0"
Info: Duplicate register "rs422:inst|p5~6" merged to single register "rs422:inst|p5~0"
Info: Duplicate register "rs422:inst|p5~8" merged to single register "rs422:inst|p5~0"
Info: Duplicate register "rs422:inst|p5~10" merged to single register "rs422:inst|p5~0"
Info: Duplicate register "rs422:inst|p5~12" merged to single register "rs422:inst|p5~0"
Info: Duplicate register "rs422:inst|p5~14" merged to single register "rs422:inst|p5~0"
Warning: Created node "rs422:inst|reduce_nor~68" as a ROM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block. Power-up state differs from the original design.
Info: Inferred 1 megafunctions from design logic
Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=256, WIDTH_A=3) from the following design logic: "rs422:inst|reduce_nor~68"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_h0j.tdf
Info: Found entity 1: altsyncram_h0j
Warning: Output pins are stuck at VCC or GND
Warning: Pin "tapg1p[1]" stuck at GND
Warning: Pin "tapg1p[0]" stuck at GND
Info: Implemented 573 device resources after synthesis - the final resource count might be different
Info: Implemented 7 input pins
Info: Implemented 98 output pins
Info: Implemented 464 logic cells
Info: Implemented 3 RAM segments
Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
Info: Processing ended: Wed Aug 09 16:09:42 2006
Info: Elapsed time: 00:00:13
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