test.fit.eqn

FPGA串口界面调试程序,用VHDL语言实现

--operation mode is normal

B1_WP[3]_lut_out = A1L021 & (B1_WP[3] $ (B1L061)) # !A1L021 & !B1L934 & (B1_WP[3] $ B1L061);
B1_WP[3] = DFFEAS(B1_WP[3]_lut_out, !GLOBAL(B1_D_enp), VCC, , , , , , );


--B1_WP[2] is rs422:inst|WP[2] at LC_X3_Y18_N9
--operation mode is normal

B1_WP[2]_lut_out = A1L321 & (B1_WP[2] $ (B1L161)) # !A1L321 & !B1L934 & (B1_WP[2] $ B1L161);
B1_WP[2] = DFFEAS(B1_WP[2]_lut_out, !GLOBAL(B1_D_enp), VCC, , , , , , );


--B1_WP[1] is rs422:inst|WP[1] at LC_X3_Y18_N4
--operation mode is normal

B1_WP[1]_lut_out = B1L934 & A1L321 & (B1_WP[1] $ B1_WP[0]) # !B1L934 & (B1_WP[1] $ B1_WP[0]);
B1_WP[1] = DFFEAS(B1_WP[1]_lut_out, !GLOBAL(B1_D_enp), VCC, , , , , , );


--B1_WP[0] is rs422:inst|WP[0] at LC_X3_Y18_N1
--operation mode is normal

B1_WP[0]_lut_out = !B1_WP[0] & (A1L321 # !B1L934);
B1_WP[0] = DFFEAS(B1_WP[0]_lut_out, !GLOBAL(B1_D_enp), VCC, , , , , , );


--B1L58 is rs422:inst|D_valid1_2~8 at LC_X7_Y18_N4
--operation mode is normal

B1L58 = !B1_D_valid1_1p & (!B1_count1_2[1] # !B1_count1_2[3] # !B1_count1_2[2]);


--D1_count0[5] is clk:inst12|count0[5] at LC_X2_Y22_N6
--operation mode is normal

D1_count0[5]_carry_eqn = (!D1L61 & D1L02) # (D1L61 & D1L12);
D1_count0[5]_lut_out = D1_count0[5]_carry_eqn $ D1_count0[5];
D1_count0[5] = DFFEAS(D1_count0[5]_lut_out, GLOBAL(G1__clk0), VCC, , , , , D1L621, );


--D1_count0[4] is clk:inst12|count0[4] at LC_X2_Y22_N5
--operation mode is arithmetic

D1_count0[4]_carry_eqn = (!D1L61 & GND) # (D1L61 & VCC);
D1_count0[4]_lut_out = D1_count0[4] $ !D1_count0[4]_carry_eqn;
D1_count0[4] = DFFEAS(D1_count0[4]_lut_out, GLOBAL(G1__clk0), VCC, , , , , D1L621, );

--D1L02 is clk:inst12|count0[4]~131 at LC_X2_Y22_N5
--operation mode is arithmetic

D1L02_cout_0 = D1_count0[4] & !D1L61;
D1L02 = CARRY(D1L02_cout_0);

--D1L12 is clk:inst12|count0[4]~131COUT1_161 at LC_X2_Y22_N5
--operation mode is arithmetic

D1L12_cout_1 = D1_count0[4] & !D1L61;
D1L12 = CARRY(D1L12_cout_1);


--D1_count0[3] is clk:inst12|count0[3] at LC_X2_Y22_N4
--operation mode is arithmetic

D1_count0[3]_lut_out = D1_count0[3] $ (D1L21);
D1_count0[3] = DFFEAS(D1_count0[3]_lut_out, GLOBAL(G1__clk0), VCC, , , , , D1L621, );

--D1L61 is clk:inst12|count0[3]~135 at LC_X2_Y22_N4
--operation mode is arithmetic

D1L61 = D1L71;


--D1_count0[0] is clk:inst12|count0[0] at LC_X2_Y22_N1
--operation mode is arithmetic

D1_count0[0]_lut_out = !D1_count0[0];
D1_count0[0] = DFFEAS(D1_count0[0]_lut_out, GLOBAL(G1__clk0), VCC, , , , , D1L621, );

--D1L6 is clk:inst12|count0[0]~139 at LC_X2_Y22_N1
--operation mode is arithmetic

D1L6_cout_0 = D1_count0[0];
D1L6 = CARRY(D1L6_cout_0);

--D1L7 is clk:inst12|count0[0]~139COUT1_156 at LC_X2_Y22_N1
--operation mode is arithmetic

D1L7_cout_1 = D1_count0[0];
D1L7 = CARRY(D1L7_cout_1);


--D1_count0[1] is clk:inst12|count0[1] at LC_X2_Y22_N2
--operation mode is arithmetic

D1_count0[1]_lut_out = D1_count0[1] $ (D1L6);
D1_count0[1] = DFFEAS(D1_count0[1]_lut_out, GLOBAL(G1__clk0), VCC, , , , , D1L621, );

--D1L9 is clk:inst12|count0[1]~143 at LC_X2_Y22_N2
--operation mode is arithmetic

D1L9_cout_0 = !D1L6 # !D1_count0[1];
D1L9 = CARRY(D1L9_cout_0);

--D1L01 is clk:inst12|count0[1]~143COUT1_158 at LC_X2_Y22_N2
--operation mode is arithmetic

D1L01_cout_1 = !D1L7 # !D1_count0[1];
D1L01 = CARRY(D1L01_cout_1);


--D1_count0[2] is clk:inst12|count0[2] at LC_X2_Y22_N3
--operation mode is arithmetic

D1_count0[2]_lut_out = D1_count0[2] $ (!D1L9);
D1_count0[2] = DFFEAS(D1_count0[2]_lut_out, GLOBAL(G1__clk0), VCC, , , , , D1L621, );

--D1L21 is clk:inst12|count0[2]~147 at LC_X2_Y22_N3
--operation mode is arithmetic

D1L21_cout_0 = D1_count0[2] & (!D1L9);
D1L21 = CARRY(D1L21_cout_0);

--D1L31 is clk:inst12|count0[2]~147COUT1_159 at LC_X2_Y22_N3
--operation mode is arithmetic

D1L31_cout_1 = D1_count0[2] & (!D1L01);
D1L31 = CARRY(D1L31_cout_1);


--D1L41 is clk:inst12|count0[2]~150 at LC_X2_Y22_N9
--operation mode is normal

D1L41 = !D1_count0[2] & (!D1_count0[0] & !D1_count0[1]);


--G1__clk0 is PLL24M:inst7|altpll:altpll_component|_clk0 at PLL_2
G1__clk0 = PLL.CLK0(.ENA(), .COMPARATOR(), .INCLK(GLOBAL(CLK40M)));


--B1_\p1:flag[0] is rs422:inst|\p1:flag[0] at LC_X7_Y15_N7
--operation mode is normal

B1_\p1:flag[0]_lut_out = B1_\p1:flag[0] & (B1_\p1:flag[1] # !B1L793) # !B1_\p1:flag[0] & !B1_\p1:flag[1] & (!RXD);
B1_\p1:flag[0] = DFFEAS(B1_\p1:flag[0]_lut_out, GLOBAL(D1_CLK_SERIAL), VCC, , , , , , );


--F1_q_a[2] is rs422:inst|altsyncram:reduce_nor_rtl_0|altsyncram_h0j:auto_generated|q_a[2] at M4K_X15_Y15
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 3
--Port A Logical Depth: 256, Port A Logical Width: 3
--Port A Input: Registered, Port A Output: Un-registered
F1_q_a[2]_PORT_A_address = BUS(B1L36, B1L56, B1L66, B1L86, B1L07, B1L27, B1L37, B1L16);
F1_q_a[2]_PORT_A_address_reg = DFFE(F1_q_a[2]_PORT_A_address, F1_q_a[2]_clock_0, , , );
F1_q_a[2]_clock_0 = GLOBAL(D1_CLK_SERIAL);
F1_q_a[2]_PORT_A_data_out = MEMORY(, , F1_q_a[2]_PORT_A_address_reg, , , , , , F1_q_a[2]_clock_0, , , , , );
F1_q_a[2] = F1_q_a[2]_PORT_A_data_out[0];

--F1_q_a[1] is rs422:inst|altsyncram:reduce_nor_rtl_0|altsyncram_h0j:auto_generated|q_a[1] at M4K_X15_Y15
F1_q_a[2]_PORT_A_address = BUS(B1L36, B1L56, B1L66, B1L86, B1L07, B1L27, B1L37, B1L16);
F1_q_a[2]_PORT_A_address_reg = DFFE(F1_q_a[2]_PORT_A_address, F1_q_a[2]_clock_0, , , );
F1_q_a[2]_clock_0 = GLOBAL(D1_CLK_SERIAL);
F1_q_a[2]_PORT_A_data_out = MEMORY(, , F1_q_a[2]_PORT_A_address_reg, , , , , , F1_q_a[2]_clock_0, , , , , );
F1_q_a[1] = F1_q_a[2]_PORT_A_data_out[2];

--F1_q_a[0] is rs422:inst|altsyncram:reduce_nor_rtl_0|altsyncram_h0j:auto_generated|q_a[0] at M4K_X15_Y15
F1_q_a[2]_PORT_A_address = BUS(B1L36, B1L56, B1L66, B1L86, B1L07, B1L27, B1L37, B1L16);
F1_q_a[2]_PORT_A_address_reg = DFFE(F1_q_a[2]_PORT_A_address, F1_q_a[2]_clock_0, , , );
F1_q_a[2]_clock_0 = GLOBAL(D1_CLK_SERIAL);
F1_q_a[2]_PORT_A_data_out = MEMORY(, , F1_q_a[2]_PORT_A_address_reg, , , , , , F1_q_a[2]_clock_0, , , , , );
F1_q_a[0] = F1_q_a[2]_PORT_A_data_out[1];


--A1L411 is rtl~656 at LC_X1_Y22_N5
--operation mode is normal

A1L411 = B1_\p1:flag[0] # B1_D_enp & F1_q_a[2];


--B1L893 is rs422:inst|reduce_nor~206 at LC_X7_Y15_N5
--operation mode is normal

B1L893 = !B1_count1_1[4] & B1_count1_1[6] & B1_count1_1[7] & !B1_count1_1[2];


--B1L993 is rs422:inst|reduce_nor~207 at LC_X8_Y15_N1
--operation mode is normal

B1L993 = B1_count1_1[3] & B1_count1_1[1] & B1_count1_1[0] & B1_count1_1[5];


--B1_\p1:flag[1] is rs422:inst|\p1:flag[1] at LC_X14_Y15_N2
--operation mode is normal

B1_\p1:flag[1]_lut_out = B1_\p1:flag[0] & (B1L531 # B1_\p1:flag[1]) # !B1_\p1:flag[0] & B1L631 & (B1_\p1:flag[1]);
B1_\p1:flag[1] = DFFEAS(B1_\p1:flag[1]_lut_out, GLOBAL(D1_CLK_SERIAL), VCC, , , , , , );


--A1L511 is rtl~657 at LC_X17_Y15_N2
--operation mode is normal

A1L511 = !F1_q_a[0] & (B1_\p1:flag[1] # RXD);


--B1L004 is rs422:inst|reduce_nor~208 at LC_X9_Y16_N6
--operation mode is normal

B1L004 = !B1_count1_1[4] & B1_count1_1[2] & !B1_count1_1[6];


--B1L104 is rs422:inst|reduce_nor~209 at LC_X8_Y15_N7
--operation mode is normal

B1_count1_1[0]_qfbk = B1_count1_1[0];
B1L104 = !B1_count1_1[7] & !B1_count1_1[5] & B1_count1_1[0]_qfbk & B1_count1_1[3];

--B1_count1_1[0] is rs422:inst|count1_1[0] at LC_X8_Y15_N7
--operation mode is normal

B1_count1_1[0] = DFFEAS(B1L104, GLOBAL(D1_CLK_SERIAL), VCC, , , B1L37, , , VCC);


--B1L793 is rs422:inst|reduce_nor~2 at LC_X9_Y16_N7
--operation mode is normal

B1L793 = B1L004 & !B1_count1_1[1] & B1L104;


--A1L611 is rtl~658 at LC_X9_Y16_N0
--operation mode is normal

A1L611 = B1_\p1:flag[1] & (!B1_\p1:flag[0]) # !B1_\p1:flag[1] & (B1_\p1:flag[0] & B1L793 # !B1_\p1:flag[0] & (!RXD));


--B1L204 is rs422:inst|reduce_nor~210 at LC_X7_Y15_N4
--operation mode is normal

B1L204 = !B1_count1_1[3] & B1_count1_1[5];


--A1L711 is rtl~659 at LC_X8_Y16_N1
--operation mode is normal

A1L711 = B1L993 # !B1_count1_1[0] & B1L204 & B1_count1_1[1];


--B1_D_busyp is rs422:inst|D_busyp at LC_X9_Y16_N5
--operation mode is normal

B1_D_busyp_qfbk = B1_D_busyp;
B1_D_busyp_lut_out = B1_D_busyp_qfbk # A1L711 & B1L893 # !A1L511;
B1_D_busyp = DFFEAS(B1_D_busyp_lut_out, GLOBAL(D1_CLK_SERIAL), VCC, , A1L611, RXD, , , B1_\p1:flag[0]);


--D1_count2[12] is clk:inst12|count2[12] at LC_X19_Y38_N3
--operation mode is arithmetic

D1_count2[12]_carry_eqn = (!D1L87 & D1L68) # (D1L87 & D1L78);
D1_count2[12]_lut_out = D1_count2[12] $ (!D1_count2[12]_carry_eqn);
D1_count2[12] = DFFEAS(D1_count2[12]_lut_out, GLOBAL(CLK40M), VCC, , , , , D1L131, );

--D1L98 is clk:inst12|count2[12]~280 at LC_X19_Y38_N3
--operation mode is arithmetic

D1L98_cout_0 = D1_count2[12] & (!D1L68);
D1L98 = CARRY(D1L98_cout_0);

--D1L09 is clk:inst12|count2[12]~280COUT1_387 at LC_X19_Y38_N3
--operation mode is arithmetic

D1L09_cout_1 = D1_count2[12] & (!D1L78);
D1L09 = CARRY(D1L09_cout_1);


--D1_count2[13] is clk:inst12|count2[13] at LC_X19_Y38_N4
--operation mode is arithmetic

D1_count2[13]_carry_eqn = (!D1L87 & D1L98) # (D1L87 & D1L09);
D1_count2[13]_lut_out = D1_count2[13] $ (D1_count2[13]_carry_eqn);
D1_count2[13] = DFFEAS(D1_count2[13]_lut_out, GLOBAL(CLK40M), VCC, , , , , D1L131, );

--D1L29 is clk:inst12|count2[13]~284 at LC_X19_Y38_N4
--operation mode is arithmetic

D1L29 = CARRY(!D1L09 # !D1_count2[13]);


--D1_count2[14] is clk:inst12|count2[14] at LC_X19_Y38_N5
--operation mode is arithmetic

D1_count2[14]_carry_eqn = D1L29;
D1_count2[14]_lut_out = D1_count2[14] $ !D1_count2[14]_carry_eqn;
D1_count2[14] = DFFEAS(D1_count2[14]_lut_out, GLOBAL(CLK40M), VCC, , , , , D1L131, );

--D1L49 is clk:inst12|count2[14]~288 at LC_X19_Y38_N5
--operation mode is arithmetic

D1L49_cout_0 = D1_count2[14] & !D1L29;
D1L49 = CARRY(D1L49_cout_0);

--D1L59 is clk:inst12|count2[14]~288COUT1_389 at LC_X19_Y38_N5
--operation mode is arithmetic

D1L59_cout_1 = D1_count2[14] & !D1L29;
D1L59 = CARRY(D1L59_cout_1);


--D1_count2[15] is clk:inst12|count2[15] at LC_X19_Y38_N6
--operation mode is arithmetic

D1_count2[15]_carry_eqn = (!D1L29 & D1L49) # (D1L29 & D1L59);
D1_count2[15]_lut_out = D1_count2[15] $ D1_count2[15]_carry_eqn;
D1_count2[15] = DFFEAS(D1_count2[15]_lut_out, GLOBAL(CLK40M), VCC, , , , , D1L131, );

--D1L79 is clk:inst12|count2[15]~292 at LC_X19_Y38_N6
--operation mode is arithmetic

D1L79_cout_0 = !D1L49 # !D1_count2[15];
D1L79 = CARRY(D1L79_cout_0);

--D1L89 is clk:inst12|count2[15]~292COUT1_391 at LC_X19_Y38_N6
--operation mode is arithmetic

D1L89_cout_1 = !D1L59 # !D1_count2[15];
D1L89 = CARRY(D1L89_cout_1);


--D1L121 is clk:inst12|LessThan~1220 at LC_X19_Y38_N9
--operation mode is normal

D1L121 = !D1_count2[12] & !D1_count2[15] & !D1_count2[14] & !D1_count2[13];


--D1_count2[8] is clk:inst12|count2[8] at LC_X19_Y39_N9
--operation mode is arithmetic

D1_count2[8]_carry_eqn = (!D1L46 & D1L57) # (D1L46 & D1L67);
D1_count2[8]_lut_out = D1_count2[8] $ !D1_count2[8]_carry_eqn;
D1_count2[8] = DFFEAS(D1_count2[8]_lut_out, GLOBAL(CLK40M), VCC, , , , , D1L131, );

--D1L87 is clk:inst12|count2[8]~296 at LC_X19_Y39_N9
--operation mode is arithmetic

D1L87 = CARRY(D1_count2[8] & !D1L67);


--D1_count2[9] is clk:inst12|count2[9] at LC_X19_Y38_N0
--operation mode is arithmetic

D1_count2[9]_carry_eqn = D1L87;
D1_count2[9]_lut_out = D1_count2[9] $ D1_count2[9]_carry_eqn;
D1_count2[9] = DFFEAS(D1_count2[9]_lut_out, GLOBAL(CLK40M), VCC, , , , , D1L131, );

--D1L08 is clk:inst12|count2[9]~300 at LC_X19_Y38_N0
--operation mode is arithmetic

D1L08_cout_0 = !D1L87 # !D1_count2[9];
D1L08 = CARRY(D1L08_cout_0);

--D1L18 is clk:inst12|count2[9]~300COUT1_381 at LC_X19_Y38_N0
--operation mode is arithmetic

D1L18_cout_1 = !D1L87 # !D1_count2[9];
D1L18 = CARRY(D1L18_cout_1);


--D1_count2[10] is clk:inst12|count2[10] at LC_X19_Y38_N1
--operation mode is arithmetic

D1_count2[10]_carry_eqn = (!D1L87 & D1L08) # (D1L87 & D1L18);
D1_count2[10]_lut_out = D1_count2[10] $ !D1_count2[10]_carry_eqn;
D1_count2[10] = DFFEAS(D1_count2[10]_lut_out, GLOBAL(CLK40M), VCC, , , , , D1L131, );

--D1L38 is clk:inst12|count2[10]~304 at LC_X19_Y38_N1
--operation mode is arithmetic

D1L38_cout_0 = D1_count2[10] & !D1L08;
D1L38 = CARRY(D1L38_cout_0);

--D1L48 is clk:inst12|count2[10]~304COUT1_383 at LC_X19_Y38_N1
--operation mode is arithmetic

D1L48_cout_1 = D1_count2[10] & !D1L18;
D1L48 = CARRY(D1L48_cout_1);


--D1_count2[11] is clk:inst12|count2[11] at LC_X19_Y38_N2
--operation mode is arithmetic

D1_count2[11]_carry_eqn = (!D1L87 & D1L38) # (D1L87 & D1L48);
D1_count2[11]_lut_out = D1_count2[11] $ (D1_count2[11]_carry_eqn);
D1_count2[11] = DFFEAS(D1_count2[11]_lut_out, GLOBAL(CLK40M), VCC, , , , , D1L131, );

--D1L68 is clk:inst12|count2[11]~308 at LC_X19_Y38_N2
--operation mode is arithmetic

D1L68_cout_0 = !D1L38 # !D1_count2[11];
D1L68 = CARRY(D1L68_cout_0);

--D1L78 is clk:inst12|count2[11]~308COUT1_385 at LC_X19_Y38_N2
--operation mode is arithmetic

D1L78_cout_1 = !D1L48 # !D1_count2[11];
D1L78 = CARRY(D1L78_cout_1);


--D1L221 is clk:inst12|LessThan~1221 at LC_X18_Y39_N5
--operation mode is normal

D1L221 = !D1_count2[11] & !D1_count2[8] & !D1_count2[10] & !D1_count2[9];


--D1_count2[3] is clk:inst12|count2[3] at LC_X19_Y39_N4
--operation mode is arithmetic

D1_count2[3]_lut_out = D1_count2[3] $ (D1L16);
D1_count2[3] = DFFEAS(D1_count2[3]_lut_out, GLOBAL(CLK40M), VCC, , , , , D1L131, );

--D1L46 is clk:inst12|count2[3]~312 at LC_X19_Y39_N4
--operation mode is arithmetic

D1L46 = CARRY(!D1L26 # !D1_count2[3]);


--D1_count2[4] is clk:inst12|count2[4] at LC_X19_Y39_N5
--operation mode is arithmetic

D1_count2[4]_carry_eqn = D1L46;
D1_count2[4]_lut_out = D1_count2[4] $ !D1_count2[4]_carry_eqn;
D1_count2[4] = DFFEAS(D1_count2[4]_lut_out, GLOBAL(CLK40M), VCC, , , , , D1L131, );

--D1L66 is clk:inst12|count2[4]~316 at LC_X19_Y39_N5
--operation mode is arithmetic