test.hier_info

FPGA串口界面调试程序,用VHDL语言实现

clk_serial => D_busy.CLK
clk_serial => temp[7].CLK
clk_serial => temp[6].CLK
clk_serial => temp[5].CLK
clk_serial => temp[4].CLK
clk_serial => temp[3].CLK
clk_serial => temp[2].CLK
clk_serial => temp[1].CLK
clk_serial => temp[0].CLK
clk_serial => Dout[7].CLK
clk_serial => Dout[6].CLK
clk_serial => Dout[5].CLK
clk_serial => Dout[4].CLK
clk_serial => Dout[3].CLK
clk_serial => Dout[2].CLK
clk_serial => Dout[1].CLK
clk_serial => Dout[0].CLK
clk_serial => count1_1[7].CLK
rxd => D_busy~1.DATAB
rxd => flag~4.OUTPUTSELECT
rxd => flag~5.OUTPUTSELECT
rxd => flag~0.OUTPUTSELECT
rxd => flag~1.OUTPUTSELECT
rxd => D_en~0.OUTPUTSELECT
rxd => D_busy~0.OUTPUTSELECT
rxd => flag~2.DATAB
rxd => temp[7].DATAIN
rxd => temp[6].DATAIN
rxd => temp[5].DATAIN
rxd => temp[4].DATAIN
rxd => temp[3].DATAIN
rxd => temp[2].DATAIN
rxd => temp[1].DATAIN
rxd => temp[0].DATAIN
dsp0_rd => dsp0_data[14]~reg0.CLK
dsp0_rd => dsp0_data[13]~reg0.CLK
dsp0_rd => dsp0_data[12]~reg0.CLK
dsp0_rd => dsp0_data[11]~reg0.CLK
dsp0_rd => dsp0_data[10]~reg0.CLK
dsp0_rd => dsp0_data[9]~reg0.CLK
dsp0_rd => dsp0_data[8]~reg0.CLK
dsp0_rd => p5~0.CLK
dsp0_rd => p5~2.CLK
dsp0_rd => p5~4.CLK
dsp0_rd => p5~6.CLK
dsp0_rd => p5~8.CLK
dsp0_rd => p5~10.CLK
dsp0_rd => p5~12.CLK
dsp0_rd => p5~14.CLK
dsp0_rd => dsp0_data[15]~reg0.CLK
dsp0_addr[0] => Mux~0.IN3
dsp0_addr[0] => Mux~1.IN19
dsp0_addr[0] => Mux~2.IN3
dsp0_addr[0] => Mux~3.IN3
dsp0_addr[0] => Mux~4.IN3
dsp0_addr[0] => Mux~5.IN3
dsp0_addr[0] => Mux~6.IN3
dsp0_addr[0] => Mux~7.IN3
dsp0_addr[0] => Mux~8.IN3
dsp0_addr[1] => Mux~0.IN2
dsp0_addr[1] => Mux~1.IN18
dsp0_addr[1] => Mux~2.IN2
dsp0_addr[1] => Mux~3.IN2
dsp0_addr[1] => Mux~4.IN2
dsp0_addr[1] => Mux~5.IN2
dsp0_addr[1] => Mux~6.IN2
dsp0_addr[1] => Mux~7.IN2
dsp0_addr[1] => Mux~8.IN2
dsp0_addr[2] => Mux~0.IN1
dsp0_addr[2] => Mux~1.IN17
dsp0_addr[2] => Mux~2.IN1
dsp0_addr[2] => Mux~3.IN1
dsp0_addr[2] => Mux~4.IN1
dsp0_addr[2] => Mux~5.IN1
dsp0_addr[2] => Mux~6.IN1
dsp0_addr[2] => Mux~7.IN1
dsp0_addr[2] => Mux~8.IN1
dsp0_addr[3] => Mux~0.IN0
dsp0_addr[3] => Mux~1.IN16
dsp0_addr[3] => Mux~2.IN0
dsp0_addr[3] => Mux~3.IN0
dsp0_addr[3] => Mux~4.IN0
dsp0_addr[3] => Mux~5.IN0
dsp0_addr[3] => Mux~6.IN0
dsp0_addr[3] => Mux~7.IN0
dsp0_addr[3] => Mux~8.IN0
dsp0_irq <= D_valid1_2.DB_MAX_OUTPUT_PORT_TYPE
dsp0_data[8] <= p5~16.DB_MAX_OUTPUT_PORT_TYPE
dsp0_data[9] <= p5~15.DB_MAX_OUTPUT_PORT_TYPE
dsp0_data[10] <= p5~13.DB_MAX_OUTPUT_PORT_TYPE
dsp0_data[11] <= p5~11.DB_MAX_OUTPUT_PORT_TYPE
dsp0_data[12] <= p5~9.DB_MAX_OUTPUT_PORT_TYPE
dsp0_data[13] <= p5~7.DB_MAX_OUTPUT_PORT_TYPE
dsp0_data[14] <= p5~5.DB_MAX_OUTPUT_PORT_TYPE
dsp0_data[15] <= p5~3.DB_MAX_OUTPUT_PORT_TYPE
Doutp[0] <= temp[0].DB_MAX_OUTPUT_PORT_TYPE
Doutp[1] <= temp[1].DB_MAX_OUTPUT_PORT_TYPE
Doutp[2] <= temp[2].DB_MAX_OUTPUT_PORT_TYPE
Doutp[3] <= temp[3].DB_MAX_OUTPUT_PORT_TYPE
Doutp[4] <= temp[4].DB_MAX_OUTPUT_PORT_TYPE
Doutp[5] <= temp[5].DB_MAX_OUTPUT_PORT_TYPE
Doutp[6] <= temp[6].DB_MAX_OUTPUT_PORT_TYPE
Doutp[7] <= temp[7].DB_MAX_OUTPUT_PORT_TYPE
D_enp <= D_en.DB_MAX_OUTPUT_PORT_TYPE
D_busyp <= D_busy.DB_MAX_OUTPUT_PORT_TYPE
WPp[0] <= WP[0].DB_MAX_OUTPUT_PORT_TYPE
WPp[1] <= WP[1].DB_MAX_OUTPUT_PORT_TYPE
WPp[2] <= WP[2].DB_MAX_OUTPUT_PORT_TYPE
WPp[3] <= WP[3].DB_MAX_OUTPUT_PORT_TYPE
STATE_1p[0] <= STATE_1[0].DB_MAX_OUTPUT_PORT_TYPE
STATE_1p[1] <= STATE_1[1].DB_MAX_OUTPUT_PORT_TYPE
Dsum1p[0] <= Dsum1[0].DB_MAX_OUTPUT_PORT_TYPE
Dsum1p[1] <= Dsum1[1].DB_MAX_OUTPUT_PORT_TYPE
Dsum1p[2] <= Dsum1[2].DB_MAX_OUTPUT_PORT_TYPE
Dsum1p[3] <= Dsum1[3].DB_MAX_OUTPUT_PORT_TYPE
Dsum1p[4] <= Dsum1[4].DB_MAX_OUTPUT_PORT_TYPE
Dsum1p[5] <= Dsum1[5].DB_MAX_OUTPUT_PORT_TYPE
Dsum1p[6] <= Dsum1[6].DB_MAX_OUTPUT_PORT_TYPE
Dsum1p[7] <= Dsum1[7].DB_MAX_OUTPUT_PORT_TYPE
LENGTH1_1P[0] <= LENGTH1_1[0].DB_MAX_OUTPUT_PORT_TYPE
LENGTH1_1P[1] <= LENGTH1_1[1].DB_MAX_OUTPUT_PORT_TYPE
LENGTH1_1P[2] <= LENGTH1_1[2].DB_MAX_OUTPUT_PORT_TYPE
LENGTH1_1P[3] <= LENGTH1_1[3].DB_MAX_OUTPUT_PORT_TYPE
LENGTH1_2P[0] <= LENGTH1_2[0].DB_MAX_OUTPUT_PORT_TYPE
LENGTH1_2P[1] <= LENGTH1_2[1].DB_MAX_OUTPUT_PORT_TYPE
LENGTH1_2P[2] <= LENGTH1_2[2].DB_MAX_OUTPUT_PORT_TYPE
LENGTH1_2P[3] <= LENGTH1_2[3].DB_MAX_OUTPUT_PORT_TYPE
count1_1p[0] <= count1_1[0].DB_MAX_OUTPUT_PORT_TYPE
count1_1p[1] <= count1_1[1].DB_MAX_OUTPUT_PORT_TYPE
count1_1p[2] <= count1_1[2].DB_MAX_OUTPUT_PORT_TYPE
count1_1p[3] <= count1_1[3].DB_MAX_OUTPUT_PORT_TYPE
count1_1p[4] <= count1_1[4].DB_MAX_OUTPUT_PORT_TYPE
count1_1p[5] <= count1_1[5].DB_MAX_OUTPUT_PORT_TYPE
count1_1p[6] <= count1_1[6].DB_MAX_OUTPUT_PORT_TYPE
count1_1p[7] <= count1_1[7].DB_MAX_OUTPUT_PORT_TYPE
count1_2p[0] <= count1_2[0].DB_MAX_OUTPUT_PORT_TYPE
count1_2p[1] <= count1_2[1].DB_MAX_OUTPUT_PORT_TYPE
count1_2p[2] <= count1_2[2].DB_MAX_OUTPUT_PORT_TYPE
count1_2p[3] <= count1_2[3].DB_MAX_OUTPUT_PORT_TYPE
D_valid1_1p <= D_valid1_1.DB_MAX_OUTPUT_PORT_TYPE
D_error1_1p <= D_error1_1.DB_MAX_OUTPUT_PORT_TYPE
data0[0] <= RAM1[0][0].DB_MAX_OUTPUT_PORT_TYPE
data0[1] <= RAM1[0][1].DB_MAX_OUTPUT_PORT_TYPE
data0[2] <= RAM1[0][2].DB_MAX_OUTPUT_PORT_TYPE
data0[3] <= RAM1[0][3].DB_MAX_OUTPUT_PORT_TYPE
data0[4] <= RAM1[0][4].DB_MAX_OUTPUT_PORT_TYPE
data0[5] <= RAM1[0][5].DB_MAX_OUTPUT_PORT_TYPE
data0[6] <= RAM1[0][6].DB_MAX_OUTPUT_PORT_TYPE
data0[7] <= RAM1[0][7].DB_MAX_OUTPUT_PORT_TYPE
data1[0] <= RAM1[1][0].DB_MAX_OUTPUT_PORT_TYPE
data1[1] <= RAM1[1][1].DB_MAX_OUTPUT_PORT_TYPE
data1[2] <= RAM1[1][2].DB_MAX_OUTPUT_PORT_TYPE
data1[3] <= RAM1[1][3].DB_MAX_OUTPUT_PORT_TYPE
data1[4] <= RAM1[1][4].DB_MAX_OUTPUT_PORT_TYPE
data1[5] <= RAM1[1][5].DB_MAX_OUTPUT_PORT_TYPE
data1[6] <= RAM1[1][6].DB_MAX_OUTPUT_PORT_TYPE
data1[7] <= RAM1[1][7].DB_MAX_OUTPUT_PORT_TYPE
data2[0] <= RAM1[2][0].DB_MAX_OUTPUT_PORT_TYPE
data2[1] <= RAM1[2][1].DB_MAX_OUTPUT_PORT_TYPE
data2[2] <= RAM1[2][2].DB_MAX_OUTPUT_PORT_TYPE
data2[3] <= RAM1[2][3].DB_MAX_OUTPUT_PORT_TYPE
data2[4] <= RAM1[2][4].DB_MAX_OUTPUT_PORT_TYPE
data2[5] <= RAM1[2][5].DB_MAX_OUTPUT_PORT_TYPE
data2[6] <= RAM1[2][6].DB_MAX_OUTPUT_PORT_TYPE
data2[7] <= RAM1[2][7].DB_MAX_OUTPUT_PORT_TYPE
data3[0] <= RAM1[3][0].DB_MAX_OUTPUT_PORT_TYPE
data3[1] <= RAM1[3][1].DB_MAX_OUTPUT_PORT_TYPE
data3[2] <= RAM1[3][2].DB_MAX_OUTPUT_PORT_TYPE
data3[3] <= RAM1[3][3].DB_MAX_OUTPUT_PORT_TYPE
data3[4] <= RAM1[3][4].DB_MAX_OUTPUT_PORT_TYPE
data3[5] <= RAM1[3][5].DB_MAX_OUTPUT_PORT_TYPE
data3[6] <= RAM1[3][6].DB_MAX_OUTPUT_PORT_TYPE
data3[7] <= RAM1[3][7].DB_MAX_OUTPUT_PORT_TYPE
data4[0] <= RAM1[4][0].DB_MAX_OUTPUT_PORT_TYPE
data4[1] <= RAM1[4][1].DB_MAX_OUTPUT_PORT_TYPE
data4[2] <= RAM1[4][2].DB_MAX_OUTPUT_PORT_TYPE
data4[3] <= RAM1[4][3].DB_MAX_OUTPUT_PORT_TYPE
data4[4] <= RAM1[4][4].DB_MAX_OUTPUT_PORT_TYPE
data4[5] <= RAM1[4][5].DB_MAX_OUTPUT_PORT_TYPE
data4[6] <= RAM1[4][6].DB_MAX_OUTPUT_PORT_TYPE
data4[7] <= RAM1[4][7].DB_MAX_OUTPUT_PORT_TYPE
data5[0] <= RAM1[5][0].DB_MAX_OUTPUT_PORT_TYPE
data5[1] <= RAM1[5][1].DB_MAX_OUTPUT_PORT_TYPE
data5[2] <= RAM1[5][2].DB_MAX_OUTPUT_PORT_TYPE
data5[3] <= RAM1[5][3].DB_MAX_OUTPUT_PORT_TYPE
data5[4] <= RAM1[5][4].DB_MAX_OUTPUT_PORT_TYPE
data5[5] <= RAM1[5][5].DB_MAX_OUTPUT_PORT_TYPE
data5[6] <= RAM1[5][6].DB_MAX_OUTPUT_PORT_TYPE
data5[7] <= RAM1[5][7].DB_MAX_OUTPUT_PORT_TYPE
tag0p <= tag0.DB_MAX_OUTPUT_PORT_TYPE
tag1p <= tag1.DB_MAX_OUTPUT_PORT_TYPE


|test|clk:inst12
CLK40M => count2[16].CLK
CLK40M => count2[15].CLK
CLK40M => count2[14].CLK
CLK40M => count2[13].CLK
CLK40M => count2[12].CLK
CLK40M => count2[11].CLK
CLK40M => count2[10].CLK
CLK40M => count2[9].CLK
CLK40M => count2[8].CLK
CLK40M => count2[7].CLK
CLK40M => count2[6].CLK
CLK40M => count2[5].CLK
CLK40M => count2[4].CLK
CLK40M => count2[3].CLK
CLK40M => count2[2].CLK
CLK40M => count2[1].CLK
CLK40M => count2[0].CLK
CLK40M => count2[17].CLK
CLK40M => clk_200k.CLK
CLK24M => count0[4].CLK
CLK24M => count0[3].CLK
CLK24M => count0[2].CLK
CLK24M => count0[1].CLK
CLK24M => count0[0].CLK
CLK24M => count1[10].CLK
CLK24M => count1[9].CLK
CLK24M => count1[8].CLK
CLK24M => count1[7].CLK
CLK24M => count1[6].CLK
CLK24M => count1[5].CLK
CLK24M => count1[4].CLK
CLK24M => count1[3].CLK
CLK24M => count1[2].CLK
CLK24M => count1[1].CLK
CLK24M => count1[0].CLK
CLK24M => count0[5].CLK
CLK24M => clk_19_2k.CLK
CLK24M => clk_480k.CLK
CLK24M => clk_12m.CLK
CLK6M <= clk_6m.DB_MAX_OUTPUT_PORT_TYPE
CLK3M <= clk_3m.DB_MAX_OUTPUT_PORT_TYPE
CLK_SERIAL <= clk_480k.DB_MAX_OUTPUT_PORT_TYPE
CLK19_2K <= clk_19_2k.DB_MAX_OUTPUT_PORT_TYPE
CLK200K <= clk_200k.DB_MAX_OUTPUT_PORT_TYPE
ROMADDR[0] <= count3[0].DB_MAX_OUTPUT_PORT_TYPE
ROMADDR[1] <= count3[1].DB_MAX_OUTPUT_PORT_TYPE
ROMADDR[2] <= count3[2].DB_MAX_OUTPUT_PORT_TYPE
ROMADDR[3] <= count3[3].DB_MAX_OUTPUT_PORT_TYPE
ROMADDR[4] <= count3[4].DB_MAX_OUTPUT_PORT_TYPE
ROMADDR[5] <= count3[5].DB_MAX_OUTPUT_PORT_TYPE


|test|PLL24M:inst7
inclk0 => altpll:altpll_component.inclk[0]
c0 <= altpll:altpll_component.clk[0]


|test|PLL24M:inst7|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => pll.CLK1
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => pll.ENA
clkena[1] => pll.ENA1
clkena[2] => pll.ENA2
clkena[3] => pll.ENA3
clkena[4] => pll.ENA4
clkena[5] => pll.ENA5
extclkena[0] => pll.EXTCLKENA
extclkena[1] => pll.EXTCLKENA1
extclkena[2] => pll.EXTCLKENA2
extclkena[3] => pll.EXTCLKENA3
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= <GND>
clk[2] <= <GND>
clk[3] <= <GND>
clk[4] <= <GND>
clk[5] <= <GND>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>