test.hier_info

FPGA串口界面调试程序,用VHDL语言实现

|test
dsp0_irq <= rs422:inst.dsp0_irq
CLK40M => rs422:inst.clk
CLK40M => clk:inst12.CLK40M
CLK40M => PLL24M:inst7.inclk0
CLK_SERIAL <= clk:inst12.CLK_SERIAL
RXD => rs422:inst.rxd
RXD => RXDOUT.DATAIN
dsp0_rd => rs422:inst.dsp0_rd
dsp0_rd => rdtest.DATAIN
dsp0_rd => RD.DATAIN
dsp0_addr[0] => rs422:inst.dsp0_addr[0]
dsp0_addr[0] => addrtest[0].DATAIN
dsp0_addr[1] => rs422:inst.dsp0_addr[1]
dsp0_addr[1] => addrtest[1].DATAIN
dsp0_addr[2] => rs422:inst.dsp0_addr[2]
dsp0_addr[2] => addrtest[2].DATAIN
dsp0_addr[3] => rs422:inst.dsp0_addr[3]
dsp0_addr[3] => addrtest[3].DATAIN
irq0 <= rs422:inst.dsp0_irq
D_enp <= rs422:inst.D_enp
D_busyp <= rs422:inst.D_busyp
rdtest <= dsp0_rd.DB_MAX_OUTPUT_PORT_TYPE
irq0test <= rs422:inst.dsp0_irq
RD <= dsp0_rd.DB_MAX_OUTPUT_PORT_TYPE
CLK200K <= clk:inst12.CLK200K
D_valid1_1p <= rs422:inst.D_valid1_1p
D_error1_1p <= rs422:inst.D_error1_1p
RXDOUT <= RXD.DB_MAX_OUTPUT_PORT_TYPE
addrtest[0] <= dsp0_addr[0].DB_MAX_OUTPUT_PORT_TYPE
addrtest[1] <= dsp0_addr[1].DB_MAX_OUTPUT_PORT_TYPE
addrtest[2] <= dsp0_addr[2].DB_MAX_OUTPUT_PORT_TYPE
addrtest[3] <= dsp0_addr[3].DB_MAX_OUTPUT_PORT_TYPE
count1_1p[0] <= rs422:inst.count1_1p[0]
count1_1p[1] <= rs422:inst.count1_1p[1]
count1_1p[2] <= rs422:inst.count1_1p[2]
count1_1p[3] <= rs422:inst.count1_1p[3]
count1_1p[4] <= rs422:inst.count1_1p[4]
count1_1p[5] <= rs422:inst.count1_1p[5]
count1_1p[6] <= rs422:inst.count1_1p[6]
count1_1p[7] <= rs422:inst.count1_1p[7]
count1_2p[0] <= rs422:inst.count1_2p[0]
count1_2p[1] <= rs422:inst.count1_2p[1]
count1_2p[2] <= rs422:inst.count1_2p[2]
count1_2p[3] <= rs422:inst.count1_2p[3]
Doutp[0] <= rs422:inst.Doutp[0]
Doutp[1] <= rs422:inst.Doutp[1]
Doutp[2] <= rs422:inst.Doutp[2]
Doutp[3] <= rs422:inst.Doutp[3]
Doutp[4] <= rs422:inst.Doutp[4]
Doutp[5] <= rs422:inst.Doutp[5]
Doutp[6] <= rs422:inst.Doutp[6]
Doutp[7] <= rs422:inst.Doutp[7]
dsp0_data[8] <= rs422:inst.dsp0_data[8]
dsp0_data[9] <= rs422:inst.dsp0_data[9]
dsp0_data[10] <= rs422:inst.dsp0_data[10]
dsp0_data[11] <= rs422:inst.dsp0_data[11]
dsp0_data[12] <= rs422:inst.dsp0_data[12]
dsp0_data[13] <= rs422:inst.dsp0_data[13]
dsp0_data[14] <= rs422:inst.dsp0_data[14]
dsp0_data[15] <= rs422:inst.dsp0_data[15]
dsp0datatest[8] <= rs422:inst.dsp0_data[8]
dsp0datatest[9] <= rs422:inst.dsp0_data[9]
dsp0datatest[10] <= rs422:inst.dsp0_data[10]
dsp0datatest[11] <= rs422:inst.dsp0_data[11]
dsp0datatest[12] <= rs422:inst.dsp0_data[12]
dsp0datatest[13] <= rs422:inst.dsp0_data[13]
dsp0datatest[14] <= rs422:inst.dsp0_data[14]
dsp0datatest[15] <= rs422:inst.dsp0_data[15]
Dsum1p[0] <= rs422:inst.Dsum1p[0]
Dsum1p[1] <= rs422:inst.Dsum1p[1]
Dsum1p[2] <= rs422:inst.Dsum1p[2]
Dsum1p[3] <= rs422:inst.Dsum1p[3]
Dsum1p[4] <= rs422:inst.Dsum1p[4]
Dsum1p[5] <= rs422:inst.Dsum1p[5]
Dsum1p[6] <= rs422:inst.Dsum1p[6]
Dsum1p[7] <= rs422:inst.Dsum1p[7]
LENGTH1_1p[0] <= rs422:inst.LENGTH1_1P[0]
LENGTH1_1p[1] <= rs422:inst.LENGTH1_1P[1]
LENGTH1_1p[2] <= rs422:inst.LENGTH1_1P[2]
LENGTH1_1p[3] <= rs422:inst.LENGTH1_1P[3]
LENGTH1_2p[0] <= rs422:inst.LENGTH1_2P[0]
LENGTH1_2p[1] <= rs422:inst.LENGTH1_2P[1]
LENGTH1_2p[2] <= rs422:inst.LENGTH1_2P[2]
LENGTH1_2p[3] <= rs422:inst.LENGTH1_2P[3]
ramtest1[0] <= rs422:inst.data2[0]
ramtest1[1] <= rs422:inst.data2[1]
ramtest1[2] <= rs422:inst.data2[2]
ramtest1[3] <= rs422:inst.data2[3]
ramtest1[4] <= rs422:inst.data2[4]
ramtest1[5] <= rs422:inst.data2[5]
ramtest1[6] <= rs422:inst.data2[6]
ramtest1[7] <= rs422:inst.data2[7]
ramtest2[0] <= rs422:inst.data3[0]
ramtest2[1] <= rs422:inst.data3[1]
ramtest2[2] <= rs422:inst.data3[2]
ramtest2[3] <= rs422:inst.data3[3]
ramtest2[4] <= rs422:inst.data3[4]
ramtest2[5] <= rs422:inst.data3[5]
ramtest2[6] <= rs422:inst.data3[6]
ramtest2[7] <= rs422:inst.data3[7]
ROMADDR[0] <= clk:inst12.ROMADDR[0]
ROMADDR[1] <= clk:inst12.ROMADDR[1]
ROMADDR[2] <= clk:inst12.ROMADDR[2]
ROMADDR[3] <= clk:inst12.ROMADDR[3]
ROMADDR[4] <= clk:inst12.ROMADDR[4]
ROMADDR[5] <= clk:inst12.ROMADDR[5]
STATE_1p[0] <= rs422:inst.STATE_1p[0]
STATE_1p[1] <= rs422:inst.STATE_1p[1]
tapg1p[0] <= <GND>
tapg1p[1] <= <GND>
WPp[0] <= rs422:inst.WPp[0]
WPp[1] <= rs422:inst.WPp[1]
WPp[2] <= rs422:inst.WPp[2]
WPp[3] <= rs422:inst.WPp[3]


|test|rs422:inst
reset => WP~20.OUTPUTSELECT
reset => WP~21.OUTPUTSELECT
reset => WP~22.OUTPUTSELECT
reset => WP~23.OUTPUTSELECT
reset => STATE_1~10.OUTPUTSELECT
reset => STATE_1~11.OUTPUTSELECT
reset => Dsum1~48.OUTPUTSELECT
reset => Dsum1~49.OUTPUTSELECT
reset => Dsum1~50.OUTPUTSELECT
reset => Dsum1~51.OUTPUTSELECT
reset => Dsum1~52.OUTPUTSELECT
reset => Dsum1~53.OUTPUTSELECT
reset => Dsum1~54.OUTPUTSELECT
reset => Dsum1~55.OUTPUTSELECT
reset => D_valid1_1~6.OUTPUTSELECT
reset => D_error1_1~5.OUTPUTSELECT
reset => LENGTH1_1~20.OUTPUTSELECT
reset => LENGTH1_1~21.OUTPUTSELECT
reset => LENGTH1_1~22.OUTPUTSELECT
reset => LENGTH1_1~23.OUTPUTSELECT
reset => LENGTH1_2~12.OUTPUTSELECT
reset => LENGTH1_2~13.OUTPUTSELECT
reset => LENGTH1_2~14.OUTPUTSELECT
reset => LENGTH1_2~15.OUTPUTSELECT
reset => count1_1~47.OUTPUTSELECT
reset => count1_1~46.OUTPUTSELECT
reset => count1_1~45.OUTPUTSELECT
reset => count1_1~44.OUTPUTSELECT
reset => count1_1~43.OUTPUTSELECT
reset => count1_1~42.OUTPUTSELECT
reset => count1_1~41.OUTPUTSELECT
reset => count1_1~40.OUTPUTSELECT
reset => flag~12.OUTPUTSELECT
reset => flag~13.OUTPUTSELECT
reset => D_en~6.OUTPUTSELECT
reset => D_busy~6.OUTPUTSELECT
reset => D_valid1_2~2.OUTPUTSELECT
reset => tag1~1.OUTPUTSELECT
reset => count1_2~12.OUTPUTSELECT
reset => count1_2~13.OUTPUTSELECT
reset => count1_2~14.OUTPUTSELECT
reset => count1_2~15.OUTPUTSELECT
reset => tag0~3.OUTPUTSELECT
reset => RAM1[0][7].ENA
reset => RAM1[0][6].ENA
reset => RAM1[0][5].ENA
reset => RAM1[0][4].ENA
reset => RAM1[0][3].ENA
reset => RAM1[0][2].ENA
reset => RAM1[0][1].ENA
reset => RAM1[0][0].ENA
reset => RAM1[1][7].ENA
reset => RAM1[1][6].ENA
reset => RAM1[1][5].ENA
reset => RAM1[1][4].ENA
reset => RAM1[1][3].ENA
reset => RAM1[1][2].ENA
reset => RAM1[1][1].ENA
reset => RAM1[1][0].ENA
reset => RAM1[2][7].ENA
reset => RAM1[2][6].ENA
reset => RAM1[2][5].ENA
reset => RAM1[2][4].ENA
reset => RAM1[2][3].ENA
reset => RAM1[2][2].ENA
reset => RAM1[2][1].ENA
reset => RAM1[2][0].ENA
reset => RAM1[3][7].ENA
reset => RAM1[3][6].ENA
reset => RAM1[3][5].ENA
reset => RAM1[3][4].ENA
reset => RAM1[3][3].ENA
reset => RAM1[3][2].ENA
reset => RAM1[3][1].ENA
reset => RAM1[3][0].ENA
reset => RAM1[4][7].ENA
reset => RAM1[4][6].ENA
reset => RAM1[4][5].ENA
reset => RAM1[4][4].ENA
reset => RAM1[4][3].ENA
reset => RAM1[4][2].ENA
reset => RAM1[4][1].ENA
reset => RAM1[4][0].ENA
reset => RAM1[5][7].ENA
reset => RAM1[5][6].ENA
reset => RAM1[5][5].ENA
reset => RAM1[5][4].ENA
reset => RAM1[5][3].ENA
reset => RAM1[5][2].ENA
reset => RAM1[5][1].ENA
reset => RAM1[5][0].ENA
reset => RAM1[6][7].ENA
reset => RAM1[6][6].ENA
reset => RAM1[6][5].ENA
reset => RAM1[6][4].ENA
reset => RAM1[6][3].ENA
reset => RAM1[6][2].ENA
reset => RAM1[6][1].ENA
reset => RAM1[6][0].ENA
reset => RAM1[7][7].ENA
reset => RAM1[7][6].ENA
reset => RAM1[7][5].ENA
reset => RAM1[7][4].ENA
reset => RAM1[7][3].ENA
reset => RAM1[7][2].ENA
reset => RAM1[7][1].ENA
reset => RAM1[7][0].ENA
reset => RAM1[8][7].ENA
reset => RAM1[8][6].ENA
reset => RAM1[8][5].ENA
reset => RAM1[8][4].ENA
reset => RAM1[8][3].ENA
reset => RAM1[8][2].ENA
reset => RAM1[8][1].ENA
reset => RAM1[8][0].ENA
reset => RAM1[9][7].ENA
reset => RAM1[9][6].ENA
reset => RAM1[9][5].ENA
reset => RAM1[9][4].ENA
reset => RAM1[9][3].ENA
reset => RAM1[9][2].ENA
reset => RAM1[9][1].ENA
reset => RAM1[9][0].ENA
reset => RAM1[10][7].ENA
reset => RAM1[10][6].ENA
reset => RAM1[10][5].ENA
reset => RAM1[10][4].ENA
reset => RAM1[10][3].ENA
reset => RAM1[10][2].ENA
reset => RAM1[10][1].ENA
reset => RAM1[10][0].ENA
reset => RAM1[11][7].ENA
reset => RAM1[11][6].ENA
reset => RAM1[11][5].ENA
reset => RAM1[11][4].ENA
reset => RAM1[11][3].ENA
reset => RAM1[11][2].ENA
reset => RAM1[11][1].ENA
reset => RAM1[11][0].ENA
reset => RAM1[12][7].ENA
reset => RAM1[12][6].ENA
reset => RAM1[12][5].ENA
reset => RAM1[12][4].ENA
reset => RAM1[12][3].ENA
reset => RAM1[12][2].ENA
reset => RAM1[12][1].ENA
reset => RAM1[12][0].ENA
reset => RAM1[13][7].ENA
reset => RAM1[13][6].ENA
reset => RAM1[13][5].ENA
reset => RAM1[13][4].ENA
reset => RAM1[13][3].ENA
reset => RAM1[13][2].ENA
reset => RAM1[13][1].ENA
reset => RAM1[13][0].ENA
reset => RAM1[14][7].ENA
reset => RAM1[14][6].ENA
reset => RAM1[14][5].ENA
reset => RAM1[14][4].ENA
reset => RAM1[14][3].ENA
reset => RAM1[14][2].ENA
reset => RAM1[14][1].ENA
reset => RAM1[14][0].ENA
clk => count1_2[2].CLK
clk => count1_2[1].CLK
clk => count1_2[0].CLK
clk => tag0.CLK
clk => count1_2[3].CLK
clk => tag1.CLK
clk => D_valid1_2.CLK
clk_serial => count1_1[6].CLK
clk_serial => count1_1[5].CLK
clk_serial => count1_1[4].CLK
clk_serial => count1_1[3].CLK
clk_serial => count1_1[2].CLK
clk_serial => count1_1[1].CLK
clk_serial => count1_1[0].CLK
clk_serial => \p1:flag[1].CLK
clk_serial => \p1:flag[0].CLK
clk_serial => D_en.CLK