test.tan.qmsg

FPGA串口界面调试程序,用VHDL语言实现

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "CLK40M register clk:inst12\|count2\[17\] register clk:inst12\|count2\[17\] 858 ps " "Info: Minimum slack time is 858 ps for clock \"CLK40M\" between source register \"clk:inst12\|count2\[17\]\" and destination register \"clk:inst12\|count2\[17\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.770 ns + Shortest register register " "Info: + Shortest register to register delay is 0.770 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk:inst12\|count2\[17\] 1 REG LC_X19_Y38_N8 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y38_N8; Fanout = 3; REG Node = 'clk:inst12\|count2\[17\]'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "" { clk:inst12|count2[17] } "NODE_NAME" } "" } } { "clk.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/clk.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.270 ns) 0.770 ns clk:inst12\|count2\[17\] 2 REG LC_X19_Y38_N8 3 " "Info: 2: + IC(0.500 ns) + CELL(0.270 ns) = 0.770 ns; Loc. = LC_X19_Y38_N8; Fanout = 3; REG Node = 'clk:inst12\|count2\[17\]'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "0.770 ns" { clk:inst12|count2[17] clk:inst12|count2[17] } "NODE_NAME" } "" } } { "clk.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/clk.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.270 ns 35.06 % " "Info: Total cell delay = 0.270 ns ( 35.06 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.500 ns 64.94 % " "Info: Total interconnect delay = 0.500 ns ( 64.94 % )" {  } {  } 0}  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "0.770 ns" { clk:inst12|count2[17] clk:inst12|count2[17] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "0.770 ns" { clk:inst12|count2[17] clk:inst12|count2[17] } { 0.0ns 0.5ns } { 0.0ns 0.27ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.088 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.088 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLK40M 25.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"CLK40M\" is 25.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destinatio