test.tan.qmsg

FPGA串口界面调试程序,用VHDL语言实现

{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'CLK40M' 6 " "Warning: Can't achieve timing requirement Clock Setup: 'CLK40M' along 6 path(s). See Report window for details." {  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "dsp0_rd " "Info: No valid register-to-register data paths exist for clock \"dsp0_rd\"" {  } {  } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "PLL24M:inst7\|altpll:altpll_component\|_clk0 register rs422:inst\|count1_1\[4\] register rs422:inst\|count1_1\[4\] 607 ps " "Info: Minimum slack time is 607 ps for clock \"PLL24M:inst7\|altpll:altpll_component\|_clk0\" between source register \"rs422:inst\|count1_1\[4\]\" and destination register \"rs422:inst\|count1_1\[4\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.519 ns + Shortest register register " "Info: + Shortest register to register delay is 0.519 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rs422:inst\|count1_1\[4\] 1 REG LC_X7_Y15_N8 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y15_N8; Fanout = 11; REG Node = 'rs422:inst\|count1_1\[4\]'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "" { rs422:inst|count1_1[4] } "NODE_NAME" } "" } } { "rs422.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/rs422.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.519 ns) 0.519 ns rs422:inst\|count1_1\[4\] 2 REG LC_X7_Y15_N8 11 " "Info: 2: + IC(0.000 ns) + CELL(0.519 ns) = 0.519 ns; Loc. = LC_X7_Y15_N8; Fanout = 11; REG Node = 'rs422:inst\|count1_1\[4\]'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "0.519 ns" { rs422:inst|count1_1[4] rs422:inst|count1_1[4] } "NODE_NAME" } "" } } { "rs422.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/rs422.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.519 ns 100.00 % " "Info: Total cell delay = 0.519 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "0.519 ns" { rs422:inst|count1_1[4] rs422:inst|count1_1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "0.519 ns" { rs422:inst|count1_1[4] rs422:inst|count1_1[4] } { 0.0ns 0.0ns } { 0.0ns 0.519ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.088 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.088 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 1.209 ns " "Info: + Latch edge is 1.209 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination PLL24M:inst7\|altpll:altpll_component\|_clk0 41.666 ns 1.209 ns  50 " "Info: Clock period of Destination clock \"PLL24M:inst7\|altpll:altpll_component\|_clk0\" is 41.666 ns with  offset of 1.209 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 1.209 ns " "Info: - Launch edge is 1.209 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source PLL24M:inst7\|altpll:altpll_component\|_clk0 41.666 ns 1.209 ns  50 " "Info: Clock period of Source clock \"PLL24M:inst7\|altpll:altpll_component\|_clk0\" is 41.666 ns with  offset of 1.209 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL24M:inst7\|altpll:altpll_component\|_clk0 destination 7.072 ns + Longest register " "Info: + Longest clock path from clock \"PLL24M:inst7\|altpll:altpll_component\|_clk0\" to destination register is 7.072 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL24M:inst7\|altpll:altpll_component\|_clk0 1 CLK PLL_2 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 19; CLK Node = 'PLL24M:inst7\|altpll:altpll_component\|_clk0'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "" { PLL24M:inst7|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.849 ns) + CELL(0.846 ns) 2.695 ns clk:inst12\|CLK_SERIAL 2 REG LC_X1_Y22_N1 37 " "Info: 2: + IC(1.849 ns) + CELL(0.846 ns) = 2.695 ns; Loc. = LC_X1_Y22_N1; Fanout = 37; REG Node = 'clk:inst12\|CLK_SERIAL'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "2.695 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL } "NODE_NAME" } "" } } { "clk.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/clk.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.733 ns) + CELL(0.644 ns) 7.072 ns rs422:inst\|count1_1\[4\] 3 REG LC_X7_Y15_N8 11 " "Info: 3: + IC(3.733 ns) + CELL(0.644 ns) = 7.072 ns; Loc. = LC_X7_Y15_N8; Fanout = 11; REG Node = 'rs422:inst\|count1_1\[4\]'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "4.377 ns" { clk:inst12|CLK_SERIAL rs422:inst|count1_1[4] } "NODE_NAME" } "" } } { "rs422.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/rs422.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.490 ns 21.07 % " "Info: Total cell delay = 1.490 ns ( 21.07 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.582 ns 78.93 % " "Info: Total interconnect delay = 5.582 ns ( 78.93 % )" {  } {  } 0}  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "7.072 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|count1_1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.072 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|count1_1[4] } { 0.0ns 1.849ns 3.733ns } { 0.0ns 0.846ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL24M:inst7\|altpll:altpll_component\|_clk0 source 7.072 ns - Shortest register " "Info: - Shortest clock path from clock \"PLL24M:inst7\|altpll:altpll_component\|_clk0\" to source register is 7.072 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL24M:inst7\|altpll:altpll_component\|_clk0 1 CLK PLL_2 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 19; CLK Node = 'PLL24M:inst7\|altpll:altpll_component\|_clk0'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "" { PLL24M:inst7|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.849 ns) + CELL(0.846 ns) 2.695 ns clk:inst12\|CLK_SERIAL 2 REG LC_X1_Y22_N1 37 " "Info: 2: + IC(1.849 ns) + CELL(0.846 ns) = 2.695 ns; Loc. = LC_X1_Y22_N1; Fanout = 37; REG Node = 'clk:inst12\|CLK_SERIAL'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "2.695 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL } "NODE_NAME" } "" } } { "clk.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/clk.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.733 ns) + CELL(0.644 ns) 7.072 ns rs422:inst\|count1_1\[4\] 3 REG LC_X7_Y15_N8 11 " "Info: 3: + IC(3.733 ns) + CELL(0.644 ns) = 7.072 ns; Loc. = LC_X7_Y15_N8; Fanout = 11; REG Node = 'rs422:inst\|count1_1\[4\]'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "4.377 ns" { clk:inst12|CLK_SERIAL rs422:inst|count1_1[4] } "NODE_NAME" } "" } } { "rs422.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/rs422.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.490 ns 21.07 % " "Info: Total cell delay = 1.490 ns ( 21.07 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.582 ns 78.93 % " "Info: Total interconnect delay = 5.582 ns ( 78.93 % )" {  } {  } 0}  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "7.072 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|count1_1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.072 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|count1_1[4] } { 0.0ns 1.849ns 3.733ns } { 0.0ns 0.846ns 0.644ns } } }  } 0}  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "7.072 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|count1_1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.072 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|count1_1[4] } { 0.0ns 1.849ns 3.733ns } { 0.0ns 0.846ns 0.644ns } } } { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "7.072 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|count1_1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.072 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|count1_1[4] } { 0.0ns 1.849ns 3.733ns } { 0.0ns 0.846ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.202 ns - " "Info: - Micro clock to output delay of source is 0.202 ns" {  } { { "rs422.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/rs422.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.114 ns + " "Info: + Micro hold delay of destination is 0.114 ns" {  } { { "rs422.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/rs422.vhd" 54 -1 0 } }  } 0}  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "7.072 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|count1_1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.072 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|count1_1[4] } { 0.0ns 1.849ns 3.733ns } { 0.0ns 0.846ns 0.644ns } } } { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "7.072 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|count1_1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.072 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|count1_1[4] } { 0.0ns 1.849ns 3.733ns } { 0.0ns 0.846ns 0.644ns } } }  } 0}  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "0.519 ns" { rs422:inst|count1_1[4] rs422:inst|count1_1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "0.519 ns" { rs422:inst|count1_1[4] rs422:inst|count1_1[4] } { 0.0ns 0.0ns } { 0.0ns 0.519ns } } } { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "7.072 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|count1_1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.072 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|count1_1[4] } { 0.0ns 1.849ns 3.733ns } { 0.0ns 0.846ns 0.644ns } } } { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "7.072 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|count1_1[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.072 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|count1_1[4] } { 0.0ns 1.849ns 3.733ns } { 0.0ns 0.846ns 0.644ns } } }  } 0}