test.tan.qmsg

FPGA串口界面调试程序,用VHDL语言实现

{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "PLL24M:inst7\|altpll:altpll_component\|_clk0 register clk:inst12\|CLK200K register clk:inst12\|count3\[5\] 2.069 ns " "Info: Slack time is 2.069 ns for clock \"PLL24M:inst7\|altpll:altpll_component\|_clk0\" between source register \"clk:inst12\|CLK200K\" and destination register \"clk:inst12\|count3\[5\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "3.935 ns + Largest register register " "Info: + Largest register to register requirement is 3.935 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "1.209 ns + " "Info: + Setup relationship between source and destination is 1.209 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 5.376 ns " "Info: + Latch edge is 5.376 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination PLL24M:inst7\|altpll:altpll_component\|_clk0 41.666 ns 22.042 ns , Inverted 50 " "Info: Clock period of Destination clock \"PLL24M:inst7\|altpll:altpll_component\|_clk0\" is 41.666 ns with , Inverted offset of 22.042 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 4.167 ns " "Info: - Launch edge is 4.167 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLK40M 25.000 ns 12.500 ns , Inverted 50 " "Info: Clock period of Source clock \"CLK40M\" is 25.000 ns with , Inverted offset of 12.500 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "2.939 ns + Largest " "Info: + Largest clock skew is 2.939 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL24M:inst7\|altpll:altpll_component\|_clk0 destination 6.840 ns + Shortest register " "Info: + Shortest clock path from clock \"PLL24M:inst7\|altpll:altpll_component\|_clk0\" to destination register is 6.840 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL24M:inst7\|altpll:altpll_component\|_clk0 1 CLK PLL_2 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 19; CLK Node = 'PLL24M:inst7\|altpll:altpll_component\|_clk0'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "" { PLL24M:inst7|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.826 ns) + CELL(0.846 ns) 2.672 ns clk:inst12\|clk_19_2k 2 REG LC_X1_Y18_N2 7 " "Info: 2: + IC(1.826 ns) + CELL(0.846 ns) = 2.672 ns; Loc. = LC_X1_Y18_N2; Fanout = 7; REG Node = 'clk:inst12\|clk_19_2k'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "2.672 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|clk_19_2k } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.524 ns) + CELL(0.644 ns) 6.840 ns clk:inst12\|count3\[5\] 3 REG LC_X18_Y40_N6 3 " "Info: 3: + IC(3.524 ns) + CELL(0.644 ns) = 6.840 ns; Loc. = LC_X18_Y40_N6; Fanout = 3; REG Node = 'clk:inst12\|count3\[5\]'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "4.168 ns" { clk:inst12|clk_19_2k clk:inst12|count3[5] } "NODE_NAME" } "" } } { "clk.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/clk.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.490 ns 21.78 % " "Info: Total cell delay = 1.490 ns ( 21.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.350 ns 78.22 % " "Info: Total interconnect delay = 5.350 ns ( 78.22 % )" {  } {  } 0}  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "6.840 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|clk_19_2k clk:inst12|count3[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.840 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|clk_19_2k clk:inst12|count3[5] } { 0.000ns 1.826ns 3.524ns } { 0.000ns 0.846ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK40M source 3.901 ns - Longest register " "Info: - Longest clock path from clock \"CLK40M\" to source register is 3.901 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.173 ns) 1.173 ns CLK40M 1 CLK PIN_A15 26 " "Info: 1: + IC(0.000 ns) + CELL(1.173 ns) = 1.173 ns; Loc. = PIN_A15; Fanout = 26; CLK Node = 'CLK40M'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "" { CLK40M } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/test.bdf" { { -88 -248 -80 -72 "CLK40M" "" } { -96 -80 -24 -80 "CLK40M" "" } { -120 16 65 -104 "CLK40M" "" } { 96 32 80 112 "CLK40M" "" } { -120 472 560 -108 "CLK40M" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.084 ns) + CELL(0.644 ns) 3.901 ns clk:inst12\|CLK200K 2 REG LC_X18_Y40_N0 9 " "Info: 2: + IC(2.084 ns) + CELL(0.644 ns) = 3.901 ns; Loc. = LC_X18_Y40_N0; Fanout = 9; REG Node = 'clk:inst12\|CLK200K'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "2.728 ns" { CLK40M clk:inst12|CLK200K } "NODE_NAME" } "" } } { "clk.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/clk.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.817 ns 46.58 % " "Info: Total cell delay = 1.817 ns ( 46.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.084 ns 53.42 % " "Info: Total interconnect delay = 2.084 ns ( 53.42 % )" {  } {  } 0}  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "3.901 ns" { CLK40M clk:inst12|CLK200K } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.901 ns" { CLK40M CLK40M~out0 clk:inst12|CLK200K } { 0.000ns 0.000ns 2.084ns } { 0.000ns 1.173ns 0.644ns } } }  } 0}  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "6.840 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|clk_19_2k clk:inst12|count3[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.840 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|clk_19_2k clk:inst12|count3[5] } { 0.000ns 1.826ns 3.524ns } { 0.000ns 0.846ns 0.644ns } } } { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "3.901 ns" { CLK40M clk:inst12|CLK200K } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.901 ns" { CLK40M CLK40M~out0 clk:inst12|CLK200K } { 0.000ns 0.000ns 2.084ns } { 0.000ns 1.173ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.202 ns - " "Info: - Micro clock to output delay of source is 0.202 ns" {  } { { "clk.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/clk.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.011 ns - " "Info: - Micro setup delay of destination is 0.011 ns" {  } { { "clk.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/clk.vhd" 21 -1 0 } }  } 0}  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "6.840 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|clk_19_2k clk:inst12|count3[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.840 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|clk_19_2k clk:inst12|count3[5] } { 0.000ns 1.826ns 3.524ns } { 0.000ns 0.846ns 0.644ns } } } { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "3.901 ns" { CLK40M clk:inst12|CLK200K } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.901 ns" { CLK40M CLK40M~out0 clk:inst12|CLK200K } { 0.000ns 0.000ns 2.084ns } { 0.000ns 1.173ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.866 ns - Longest register register " "Info: - Longest register to register delay is 1.866 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk:inst12\|CLK200K 1 REG LC_X18_Y40_N0 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y40_N0; Fanout = 9; REG Node = 'clk:inst12\|CLK200K'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "" { clk:inst12|CLK200K } "NODE_NAME" } "" } } { "clk.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/clk.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.512 ns) + CELL(0.100 ns) 0.612 ns rtl~32 2 COMB LC_X18_Y40_N7 6 " "Info: 2: + IC(0.512 ns) + CELL(0.100 ns) = 0.612 ns; Loc. = LC_X18_Y40_N7; Fanout = 6; COMB Node = 'rtl~32'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "0.612 ns" { clk:inst12|CLK200K rtl~32 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.420 ns) + CELL(0.834 ns) 1.866 ns clk:inst12\|count3\[5\] 3 REG LC_X18_Y40_N6 3 " "Info: 3: + IC(0.420 ns) + CELL(0.834 ns) = 1.866 ns; Loc. = LC_X18_Y40_N6; Fanout = 3; REG Node = 'clk:inst12\|count3\[5\]'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "1.254 ns" { rtl~32 clk:inst12|count3[5] } "NODE_NAME" } "" } } { "clk.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/clk.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.934 ns 50.05 % " "Info: Total cell delay = 0.934 ns ( 50.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.932 ns 49.95 % " "Info: Total interconnect delay = 0.932 ns ( 49.95 % )" {  } {  } 0}  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "1.866 ns" { clk:inst12|CLK200K rtl~32 clk:inst12|count3[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.866 ns" { clk:inst12|CLK200K rtl~32 clk:inst12|count3[5] } { 0.000ns 0.512ns 0.420ns } { 0.000ns 0.100ns 0.834ns } } }  } 0}  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "6.840 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|clk_19_2k clk:inst12|count3[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.840 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|clk_19_2k clk:inst12|count3[5] } { 0.000ns 1.826ns 3.524ns } { 0.000ns 0.846ns 0.644ns } } } { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "3.901 ns" { CLK40M clk:inst12|CLK200K } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.901 ns" { CLK40M CLK40M~out0 clk:inst12|CLK200K } { 0.000ns 0.000ns 2.084ns } { 0.000ns 1.173ns 0.644ns } } } { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "1.866 ns" { clk:inst12|CLK200K rtl~32 clk:inst12|count3[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.866 ns" { clk:inst12|CLK200K rtl~32 clk:inst12|count3[5] } { 0.000ns 0.512ns 0.420ns } { 0.000ns 0.100ns 0.834ns } } }  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLK40M register rs422:inst\|D_valid1_1p register rs422:inst\|count1_2\[3\] -7.688 ns " "Info: Slack time is -7.688 ns for clock \"CLK40M\" between source register \"rs422:inst\|D_valid1_1p\" and destination register \"rs422:inst\|count1_2\[3\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-4.972 ns + Largest register register " "Info: + Largest register to register requirement is -4.972 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "2.957 ns + " "Info: + Setup relationship between source and destination is 2.957 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 8.333 ns " "Info: + Latch edge is 8.333 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLK40M 25.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"CLK40M\" is 25.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 5.376 ns " "Info: - Launch edge is 5.376 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source PLL24M:inst7\|altpll:altpll_component\|_clk0 41.666 ns 22.042 ns , Inverted 50 " "Info: Clock period of Source clock \"PLL24M:inst7\|altpll:altpll_component\|_clk0\" is 41.666 ns with , Inverted offset of 22.042 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-7.716 ns + Largest " "Info: + Largest clock skew is -7.716 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK40M destination 4.014 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK40M\" to destination register is 4.014 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.173 ns) 1.173 ns CLK40M 1 CLK PIN_A15 26 " "Info: 1: + IC(0.000 ns) + CELL(1.173 ns) = 1.173 ns; Loc. = PIN_A15; Fanout = 26; CLK Node = 'CLK40M'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "" { CLK40M } "NODE_NAME" } "" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/test.bdf" { { -88 -248 -80 -72 "CLK40M" "" } { -96 -80 -24 -80 "CLK40M" "" } { -120 16 65 -104 "CLK40M" "" } { 96 32 80 112 "CLK40M" "" } { -120 472 560 -108 "CLK40M" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.197 ns) + CELL(0.644 ns) 4.014 ns rs422:inst\|count1_2\[3\] 2 REG LC_X2_Y18_N7 5 " "Info: 2: + IC(2.197 ns) + CELL(0.644 ns) = 4.014 ns; Loc. = LC_X2_Y18_N7; Fanout = 5; REG Node = 'rs422:inst\|count1_2\[3\]'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "2.841 ns" { CLK40M rs422:inst|count1_2[3] } "NODE_NAME" } "" } } { "rs422.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/rs422.vhd" 55 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.817 ns 45.27 % " "Info: Total cell delay = 1.817 ns ( 45.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.197 ns 54.73 % " "Info: Total interconnect delay = 2.197 ns ( 54.73 % )" {  } {  } 0}  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "4.014 ns" { CLK40M rs422:inst|count1_2[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.014 ns" { CLK40M CLK40M~out0 rs422:inst|count1_2[3] } { 0.000ns 0.000ns 2.197ns } { 0.000ns 1.173ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL24M:inst7\|altpll:altpll_component\|_clk0 source 11.730 ns - Longest register " "Info: - Longest clock path from clock \"PLL24M:inst7\|altpll:altpll_component\|_clk0\" to source register is 11.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL24M:inst7\|altpll:altpll_component\|_clk0 1 CLK PLL_2 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 19; CLK Node = 'PLL24M:inst7\|altpll:altpll_component\|_clk0'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "" { PLL24M:inst7|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.849 ns) + CELL(0.846 ns) 2.695 ns clk:inst12\|CLK_SERIAL 2 REG LC_X1_Y22_N1 37 " "Info: 2: + IC(1.849 ns) + CELL(0.846 ns) = 2.695 ns; Loc. = LC_X1_Y22_N1; Fanout = 37; REG Node = 'clk:inst12\|CLK_SERIAL'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "2.695 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL } "NODE_NAME" } "" } } { "clk.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/clk.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.797 ns) + CELL(0.846 ns) 7.338 ns rs422:inst\|D_enp 3 REG LC_X1_Y22_N2 146 " "Info: 3: + IC(3.797 ns) + CELL(0.846 ns) = 7.338 ns; Loc. = LC_X1_Y22_N2; Fanout = 146; REG Node = 'rs422:inst\|D_enp'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "4.643 ns" { clk:inst12|CLK_SERIAL rs422:inst|D_enp } "NODE_NAME" } "" } } { "rs422.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/rs422.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.748 ns) + CELL(0.644 ns) 11.730 ns rs422:inst\|D_valid1_1p 4 REG LC_X7_Y18_N6 7 " "Info: 4: + IC(3.748 ns) + CELL(0.644 ns) = 11.730 ns; Loc. = LC_X7_Y18_N6; Fanout = 7; REG Node = 'rs422:inst\|D_valid1_1p'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "4.392 ns" { rs422:inst|D_enp rs422:inst|D_valid1_1p } "NODE_NAME" } "" } } { "rs422.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/rs422.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns 19.91 % " "Info: Total cell delay = 2.336 ns ( 19.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.394 ns 80.09 % " "Info: Total interconnect delay = 9.394 ns ( 80.09 % )" {  } {  } 0}  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "11.730 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|D_enp rs422:inst|D_valid1_1p } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.730 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|D_enp rs422:inst|D_valid1_1p } { 0.000ns 1.849ns 3.797ns 3.748ns } { 0.000ns 0.846ns 0.846ns 0.644ns } } }  } 0}  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "4.014 ns" { CLK40M rs422:inst|count1_2[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.014 ns" { CLK40M CLK40M~out0 rs422:inst|count1_2[3] } { 0.000ns 0.000ns 2.197ns } { 0.000ns 1.173ns 0.644ns } } } { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "11.730 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|D_enp rs422:inst|D_valid1_1p } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.730 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|D_enp rs422:inst|D_valid1_1p } { 0.000ns 1.849ns 3.797ns 3.748ns } { 0.000ns 0.846ns 0.846ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.202 ns - " "Info: - Micro clock to output delay of source is 0.202 ns" {  } { { "rs422.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/rs422.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.011 ns - " "Info: - Micro setup delay of destination is 0.011 ns" {  } { { "rs422.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/rs422.vhd" 55 -1 0 } }  } 0}  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "4.014 ns" { CLK40M rs422:inst|count1_2[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.014 ns" { CLK40M CLK40M~out0 rs422:inst|count1_2[3] } { 0.000ns 0.000ns 2.197ns } { 0.000ns 1.173ns 0.644ns } } } { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "11.730 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|D_enp rs422:inst|D_valid1_1p } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.730 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|D_enp rs422:inst|D_valid1_1p } { 0.000ns 1.849ns 3.797ns 3.748ns } { 0.000ns 0.846ns 0.846ns 0.644ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.716 ns - Longest register register " "Info: - Longest register to register delay is 2.716 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rs422:inst\|D_valid1_1p 1 REG LC_X7_Y18_N6 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y18_N6; Fanout = 7; REG Node = 'rs422:inst\|D_valid1_1p'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "" { rs422:inst|D_valid1_1p } "NODE_NAME" } "" } } { "rs422.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/rs422.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.216 ns) + CELL(0.244 ns) 1.460 ns rtl~13 2 COMB LC_X2_Y18_N4 4 " "Info: 2: + IC(1.216 ns) + CELL(0.244 ns) = 1.460 ns; Loc. = LC_X2_Y18_N4; Fanout = 4; COMB Node = 'rtl~13'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "1.460 ns" { rs422:inst|D_valid1_1p rtl~13 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.834 ns) 2.716 ns rs422:inst\|count1_2\[3\] 3 REG LC_X2_Y18_N7 5 " "Info: 3: + IC(0.422 ns) + CELL(0.834 ns) = 2.716 ns; Loc. = LC_X2_Y18_N7; Fanout = 5; REG Node = 'rs422:inst\|count1_2\[3\]'" {  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "1.256 ns" { rtl~13 rs422:inst|count1_2[3] } "NODE_NAME" } "" } } { "rs422.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/rs422.vhd" 55 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.078 ns 39.69 % " "Info: Total cell delay = 1.078 ns ( 39.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.638 ns 60.31 % " "Info: Total interconnect delay = 1.638 ns ( 60.31 % )" {  } {  } 0}  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "2.716 ns" { rs422:inst|D_valid1_1p rtl~13 rs422:inst|count1_2[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.716 ns" { rs422:inst|D_valid1_1p rtl~13 rs422:inst|count1_2[3] } { 0.000ns 1.216ns 0.422ns } { 0.000ns 0.244ns 0.834ns } } }  } 0}  } { { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "4.014 ns" { CLK40M rs422:inst|count1_2[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.014 ns" { CLK40M CLK40M~out0 rs422:inst|count1_2[3] } { 0.000ns 0.000ns 2.197ns } { 0.000ns 1.173ns 0.644ns } } } { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "11.730 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|D_enp rs422:inst|D_valid1_1p } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.730 ns" { PLL24M:inst7|altpll:altpll_component|_clk0 clk:inst12|CLK_SERIAL rs422:inst|D_enp rs422:inst|D_valid1_1p } { 0.000ns 1.849ns 3.797ns 3.748ns } { 0.000ns 0.846ns 0.846ns 0.644ns } } } { "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" "" { Report "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test_cmp.qrpt" Compiler "test" "UNKNOWN" "V1" "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/db/test.quartus_db" { Floorplan "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/" "" "2.716 ns" { rs422:inst|D_valid1_1p rtl~13 rs422:inst|count1_2[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.716 ns" { rs422:inst|D_valid1_1p rtl~13 rs422:inst|count1_2[3] } { 0.000ns 1.216ns 0.422ns } { 0.000ns 0.244ns 0.834ns } } }  } 0}