test.tan.qmsg

FPGA串口界面调试程序,用VHDL语言实现

{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "dsp0_rd " "Info: Assuming node \"dsp0_rd\" is an undefined clock" {  } { { "test.bdf" "" { Schematic "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/test.bdf" { { -56 -248 -80 -40 "dsp0_rd" "" } { -64 -80 -7 -48 "DSP0_RD" "" } { -72 472 560 -60 "DSP0_RD" "" } { 296 1034 1168 308 "DSP0_RD" "" } { 480 1015 1168 492 "DSP0_RD" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dsp0_rd" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk:inst12\|clk_19_2k " "Info: Detected ripple clock \"clk:inst12\|clk_19_2k\" as buffer" {  } { { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk:inst12\|clk_19_2k" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "rs422:inst\|D_enp " "Info: Detected ripple clock \"rs422:inst\|D_enp\" as buffer" {  } { { "rs422.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/rs422.vhd" 16 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rs422:inst\|D_enp" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "clk:inst12\|CLK_SERIAL " "Info: Detected ripple clock \"clk:inst12\|CLK_SERIAL\" as buffer" {  } { { "clk.vhd" "" { Text "C:/Documents and Settings/uesr/桌面/ML9串口调试/FPGA串口界面调试程序/clk.vhd" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk:inst12\|CLK_SERIAL" } } } }  } 0}  } {  } 0}