test.fit.summary

FPGA串口界面调试程序,用VHDL语言实现

Flow Status : Successful - Wed Aug 09 16:10:19 2006
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : test
Top-level Entity Name : test
Family : Stratix
Device : EP1S20F672I7
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 381 / 18,460 ( 2 % )
Total pins : 105 / 427 ( 24 % )
Total virtual pins : 0
Total memory bits : 768 / 1,669,248 ( < 1 % )
DSP block 9-bit elements : 0 / 80 ( 0 % )
Total PLLs : 1 / 6 ( 16 % )
Total DLLs : 0 / 2 ( 0 % )