📄 test.vwf

📁 FPGA串口界面调试程序,用VHDL语言实现
💻 VWF
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	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("rdtest")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ROMADDR[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ROMADDR[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ROMADDR[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ROMADDR[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ROMADDR[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ROMADDR[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("RXD")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[0][7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[0][6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[0][5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[0][4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[0][3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[0][2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[0][1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[0][0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[1][7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[1][6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[1][5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[1][4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[1][3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[1][2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[1][1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[1][0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[2][7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[2][6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[2][5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[2][4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[2][3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[2][2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[2][1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[2][0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[3][7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[3][6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[3][5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[3][4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[3][3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[3][2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[3][1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[3][0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[4][7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[4][6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[4][5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[4][4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[4][3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[4][2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[4][1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[4][0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[5][7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[5][6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[5][5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[5][4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[5][3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[5][2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[5][1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|RAM1[5][0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("CLK200K")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("count1_1p[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("count1_1p[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("count1_1p[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("count1_1p[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("count1_1p[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("count1_1p[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("count1_1p[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("count1_1p[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("count1_2p[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("count1_2p[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("count1_2p[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("count1_2p[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("D_busyp")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("dsp0datatest[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("dsp0datatest[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("dsp0datatest[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("dsp0datatest[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("dsp0datatest[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("dsp0datatest[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("dsp0datatest[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("dsp0datatest[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|count1_1[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|count1_1[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|count1_1[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|count1_1[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|count1_1[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|count1_1[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|count1_1[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|count1_1[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|count1_2[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|count1_2[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|count1_2[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|count1_2[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|D_busy")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST("rs422:inst|D_en")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 15000000.0;
	}
}

TRANSITION_LIST(
上一页 1 2 3 45
💿 文件大小 927 K
👤 上传用户 yuanshuai440
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#FPGA #VHDL #串口 #调试
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