📄 test.vwf

📁 FPGA串口界面调试程序,用VHDL语言实现
💻 VWF
📖 第 1 页 / 共 5 页
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	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("LENGTH1_1p[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LENGTH1_1p";
}

SIGNAL("LENGTH1_1p[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LENGTH1_1p";
}

SIGNAL("LENGTH1_1p[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LENGTH1_1p";
}

SIGNAL("LENGTH1_1p[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LENGTH1_1p";
}

SIGNAL("LENGTH1_2p")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 4;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("LENGTH1_2p[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LENGTH1_2p";
}

SIGNAL("LENGTH1_2p[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LENGTH1_2p";
}

SIGNAL("LENGTH1_2p[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LENGTH1_2p";
}

SIGNAL("LENGTH1_2p[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "LENGTH1_2p";
}

GROUP("dsp0_addr")
{
	MEMBERS = "dsp0_addr[3]", "dsp0_addr[2]", "dsp0_addr[1]", "dsp0_addr[0]";
}

SIGNAL("WPp")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 4;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("WPp[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "WPp";
}

SIGNAL("WPp[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "WPp";
}

SIGNAL("WPp[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "WPp";
}

SIGNAL("WPp[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "WPp";
}

SIGNAL("rs422:inst|WP")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 4;
	LSB_INDEX = 0;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("rs422:inst|WP[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "rs422:inst|WP";
}

SIGNAL("rs422:inst|WP[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "rs422:inst|WP";
}

SIGNAL("rs422:inst|WP[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "rs422:inst|WP";
}

SIGNAL("rs422:inst|WP[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "rs422:inst|WP";
}

TRANSITION_LIST("D_enp")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("dsp0_addr[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 8974490.0;
		LEVEL 1 FOR 800000.0;
		LEVEL 0 FOR 4224365.0;
		LEVEL 1 FOR 800000.0;
		LEVEL 0 FOR 201145.0;
	}
}

TRANSITION_LIST("dsp0_addr[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 8574490.0;
		LEVEL 1 FOR 400000.0;
		NODE
		{
			REPEAT = 1;
			LEVEL 0 FOR 400000.0;
			LEVEL 1 FOR 400000.0;
		}
		LEVEL 0 FOR 3824365.0;
		LEVEL 1 FOR 400000.0;
		NODE
		{
			REPEAT = 1;
			LEVEL 0 FOR 400000.0;
			LEVEL 1 FOR 400000.0;
		}
		LEVEL 0 FOR 201145.0;
	}
}

TRANSITION_LIST("dsp0_addr[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 8374490.0;
		LEVEL 1 FOR 200000.0;
		NODE
		{
			REPEAT = 3;
			LEVEL 0 FOR 200000.0;
			LEVEL 1 FOR 200000.0;
		}
		LEVEL 0 FOR 3624365.0;
		LEVEL 1 FOR 200000.0;
		NODE
		{
			REPEAT = 3;
			LEVEL 0 FOR 200000.0;
			LEVEL 1 FOR 200000.0;
		}
		LEVEL 0 FOR 201145.0;
	}
}

TRANSITION_LIST("dsp0_addr[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 8274490.0;
		LEVEL 1 FOR 100000.0;
		NODE
		{
			REPEAT = 7;
			LEVEL 0 FOR 100000.0;
			LEVEL 1 FOR 100000.0;
		}
		LEVEL 0 FOR 3524365.0;
		LEVEL 1 FOR 100000.0;
		NODE
		{
			REPEAT = 7;
			LEVEL 0 FOR 100000.0;
			LEVEL 1 FOR 100000.0;
		}
		LEVEL 0 FOR 201145.0;
	}
}

TRANSITION_LIST("dsp0_rd")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 8168550.0;
		LEVEL 0 FOR 9490.0;
		LEVEL 1 FOR 103135.0;
		LEVEL 0 FOR 9490.0;
		LEVEL 1 FOR 90695.0;
		LEVEL 0 FOR 9490.0;
		LEVEL 1 FOR 89635.0;
		LEVEL 0 FOR 7385.0;
		LEVEL 1 FOR 92800.0;
		LEVEL 0 FOR 8435.0;
		LEVEL 1 FOR 92800.0;
		LEVEL 0 FOR 7070.0;
		LEVEL 1 FOR 92800.0;
		LEVEL 0 FOR 8435.0;
		LEVEL 1 FOR 90690.0;
		LEVEL 0 FOR 9175.0;
		LEVEL 1 FOR 91750.0;
		LEVEL 0 FOR 7380.0;
		LEVEL 1 FOR 91745.0;
		LEVEL 0 FOR 8435.0;
		LEVEL 1 FOR 92805.0;
		LEVEL 0 FOR 9490.0;
		LEVEL 1 FOR 90690.0;
		LEVEL 0 FOR 7385.0;
		LEVEL 1 FOR 93325.0;
		LEVEL 0 FOR 6330.0;
		LEVEL 1 FOR 93855.0;
		LEVEL 0 FOR 8435.0;
		LEVEL 1 FOR 94910.0;
		LEVEL 0 FOR 8435.0;
		LEVEL 1 FOR 91750.0;
		LEVEL 0 FOR 7380.0;
		LEVEL 1 FOR 3498740.0;
		LEVEL 0 FOR 9490.0;
		LEVEL 1 FOR 103135.0;
		LEVEL 0 FOR 9490.0;
		LEVEL 1 FOR 90695.0;
		LEVEL 0 FOR 9490.0;
		LEVEL 1 FOR 89635.0;
		LEVEL 0 FOR 7385.0;
		LEVEL 1 FOR 92800.0;
		LEVEL 0 FOR 8435.0;
		LEVEL 1 FOR 92800.0;
		LEVEL 0 FOR 7070.0;
		LEVEL 1 FOR 92800.0;
		LEVEL 0 FOR 8435.0;
		LEVEL 1 FOR 90690.0;
		LEVEL 0 FOR 9175.0;
		LEVEL 1 FOR 91750.0;
		LEVEL 0 FOR 7380.0;
		LEVEL 1 FOR 91745.0;
		LEVEL 0 FOR 8435.0;
		LEVEL 1 FOR 92805.0;
		LEVEL 0 FOR 9490.0;
		LEVEL 1 FOR 90690.0;
		LEVEL 0 FOR 7385.0;
		LEVEL 1 FOR 93325.0;
		LEVEL 0 FOR 6330.0;
		LEVEL 1 FOR 93855.0;
		LEVEL 0 FOR 8435.0;
		LEVEL 1 FOR 94910.0;
		LEVEL 0 FOR 8435.0;
		LEVEL 1 FOR 91750.0;
		LEVEL 0 FOR 7380.0;
		LEVEL 1 FOR 281460.0;
	}
}

TRANSITION_LIST("dsp0_data[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("dsp0_data[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("dsp0_data[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("dsp0_data[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("dsp0_data[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("dsp0_data[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("dsp0_data[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("dsp0_data[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("Doutp[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("Doutp[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("Doutp[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("Doutp[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("Doutp[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("Doutp[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("Doutp[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("Doutp[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("Dsum1p[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("Dsum1p[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("Dsum1p[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("Dsum1p[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("Dsum1p[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("Dsum1p[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("Dsum1p[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("Dsum1p[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("STATE_1p[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("STATE_1p[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("addrtest[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("addrtest[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("addrtest[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("addrtest[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("CLK40M")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 600000;
			LEVEL 0 FOR 12.5;
			LEVEL 1 FOR 12.5;
		}
	}
}

TRANSITION_LIST("CLK_SERIAL")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("dsp0_irq")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("irq0")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("irq0test")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ramtest1[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ramtest1[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ramtest1[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ramtest1[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ramtest1[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ramtest1[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ramtest1[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ramtest1[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ramtest2[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ramtest2[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ramtest2[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ramtest2[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ramtest2[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ramtest2[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ramtest2[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("ramtest2[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 15000000.0;
	}
}

TRANSITION_LIST("RD")
{
	NODE
💿 文件大小 927 K
👤 上传用户 yuanshuai440
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#FPGA #VHDL #串口 #调试
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