clk.vhd

FPGA串口界面调试程序,用VHDL语言实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity clk is
port(
     CLK40M,CLK24M:IN STD_LOGIC;  --16，24MHz
    
     CLK6M,CLK3M:OUT STD_LOGIC;
     CLK_SERIAL,CLK19_2K:OUT STD_LOGIC; --串口通信时钟，480kHz=19.2kbps*25
     CLK200K:OUT STD_LOGIC;
     ROMADDR:OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
     );
end clk;

architecture rtl of clk is
signal count0:integer range 0 to 63;
signal count1:integer range 0 to 2047;
signal count2:integer range 0 to 262143;
signal count3:std_logic_vector(5 downto 0);
signal clk_16m,clk_12m,clk_6m,clk_8m,clk_3m,clk_480k,clk_19_2k,clk_200k:std_logic;
signal tag0:std_logic;
begin

process(clk24m)
begin
   if(clk24m'event and clk24m='0')then
       clk_12m<=not clk_12m;
   end if;
end process;

process(clk_12m,clk_6m)
begin
   if(clk_12m'event and clk_12m='1')then
      clk_6m<=not clk_6m;
   end if;
end process;
   clk6m<=clk_6m;

process(clk_6m,clk_3m)
begin
   if(clk_6m'event and clk_6m='1')then
      clk_3m<=not clk_3m;
   end if;
end process;
   clk3m<=clk_3m;

process(clk24m)
begin
   if(clk24m'event and clk24m='1')then
      if(count0<49)then
         count0<=count0+1;
      else
         count0<=0;
      end if;
   end if;
end process;

process(clk24m,count0)
begin
   if(clk24m'event and clk24m='0')then
      if(count0<=24)then
         clk_480k<='0';
      else
         clk_480k<='1';
      end if;
   end if;
end process;
CLK_SERIAL<=clk_480k;

process(clk24m)
begin
   if(clk24m'event and clk24m='1')then
      if(count1<1249)then
         count1<=count1+1;
      else
         count1<=0;
      end if;
   end if;
end process;

process(clk24m,count1)
begin
   if(clk24m'event and clk24m='0')then
      if(count1<750)then
         clk_19_2k<='0';
      else
         clk_19_2k<='1';
      end if;
   end if;
end process;
CLK19_2K<=clk_19_2k;

process(CLK40M)
begin
   if(clk40m'event and clk40m='1')then
      if(count2<199999)then
         count2<=count2+1;
      else
         count2<=0;
      end if;
   end if;
end process;

process(CLK40M,count2)
begin
   if(clk40m'event and clk40m='0')then
      if(count2<200)then
         clk_200k<='0';
      else
         clk_200k<='1';
      end if;
   end if;
end process;
CLK200K<=clk_200k;

process(clk_200k,clk_19_2k)
begin
   if(clk_19_2k'event and clk_19_2k='0') then
      if(clk_200k='0') then
         tag0<='1';
         count3<="000000";
      elsif(clk_200k='1' and tag0='1') then
         if(count3<60) then
            count3<=count3+1;
         else
            count3<="000000";
            tag0<='0';
         end if;
      end if;
   end if;
end process;
ROMADDR<=count3;

end rtl;