des_top.v

有效的改进3-DES算法的执行速度

// *******************************************************//
//
//  DES_TOP 
//  DES Top Level module 
//  Author:
//  Date  ：2005/11/04
//
// *******************************************************//

module DES_TOP (
                des_clk    ,
                rst_n      ,
                load       ,
                des_in     , 
                key        , 
                mode       ,
                des_out    ,
                ready
                );

input           des_clk    ;
input           rst_n      ;                
input   [63:0]  des_in     ;
input   [63:0]  key        ;
input           mode       ;
input           load       ;
                           
output  [63:0]  des_out    ;
output          ready      ;

wire    [1:64]  IP, FP;
wire    [55:0]  key_tmp;
reg     [63:0]  des_in_r;
reg     [55:0]  key_r;
reg     [63:0]  des_out;
reg     [1:32]  L0, L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, L15;
reg     [1:32]  R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15;
wire    [1:32]  out0, out1, out2, out3, out4, out5, out6, out7, out8, out9, out10, out11, out12, out13, out14, out15;
wire    [1:48]  K1, K2, K3, K4, K5, K6, K7, K8, K9;
wire    [1:48]  K10, K11, K12, K13, K14, K15, K16;

reg     [3:0 ]  sta_cnt;
reg     [3:0 ]  sto_cnt;
reg             load_ff1;
reg             sta;
reg             sto;
reg             ready;


// load signal delay one clock
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        load_ff1 <= 4'b0;
    else
        load_ff1 <= #1 load;
end
//detect pose edge of load 
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        sta <= 4'b0;
    else if((load==1'b1)&&(load_ff1==1'b0))
        sta <= #1 1'b1;
    else if(sta_cnt==4'b1111)
        sta <= #1 1'b0;
    else
        sta <= #1 sta ;
end
//count 16 clock
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        sta_cnt <= 4'b0;
    else if(sta==1'b1)
        sta_cnt <= #1 sta_cnt + 4'b1;
    else
        sta_cnt <= #1 sta_cnt;
end
// detect neg edge of load signal
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        sto <= 4'b0;
    else if((load==1'b0)&&(load_ff1==1'b1))
        sto <= #1 1'b1;
    else if(sto_cnt==4'b1111)
        sto <= #1 1'b0;
    else
        sto <= #1 sto ;
end
// count 16 clock
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        sto_cnt <= 4'b0;
    else if(sto==1'b1)
        sto_cnt <= #1 sto_cnt + 4'b1;
    else
        sto_cnt <= #1 sto_cnt;
end
// when load change 0 to 1,wait 16 clock,ready is 1;
// when load change 1 to 0,wait 16 clock,ready is 0.
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        ready <= 4'b0;
    else if(sta_cnt==4'b1111)
        ready <= #1 1'b1;
    else if(sto_cnt==4'b1111)
        ready <= #1 1'b0;
    else
        ready <= #1 ready;
end
        
// key has 64 bit,thereinto 56,48,40,32,24,16,8,0 bit is parity bit,
// drop out of DES operation
assign key_tmp[55:0] = {key[63:57],key[55:49],key[47:41],key[39:33],
                        key[31:25],key[23:17],key[15:9] ,key[7:1]};

// Register the 56 bit K
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        key_r <= 56'b0;
    else if(load==1'b1)
        key_r <= #1 key_tmp;
    else
        key_r <= #1 key_r ;
end     

// Register the 64 bit input
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        des_in_r <= 56'b0;
    else if(load==1'b1)
        des_in_r <= #1 des_in;
    else
        des_in_r <= #1 des_in_r;
end     

// Perform the initial permutationi with the registerd des_in
assign IP[1:64] = {     des_in_r[06], des_in_r[14], des_in_r[22], des_in_r[30], des_in_r[38], des_in_r[46],
                        des_in_r[54], des_in_r[62], des_in_r[04], des_in_r[12], des_in_r[20], des_in_r[28],
                        des_in_r[36], des_in_r[44], des_in_r[52], des_in_r[60], des_in_r[02], des_in_r[10], 
                        des_in_r[18], des_in_r[26], des_in_r[34], des_in_r[42], des_in_r[50], des_in_r[58], 
                        des_in_r[00], des_in_r[08], des_in_r[16], des_in_r[24], des_in_r[32], des_in_r[40], 
                        des_in_r[48], des_in_r[56], des_in_r[07], des_in_r[15], des_in_r[23], des_in_r[31], 
                        des_in_r[39], des_in_r[47], des_in_r[55], des_in_r[63], des_in_r[05], des_in_r[13],
                        des_in_r[21], des_in_r[29], des_in_r[37], des_in_r[45], des_in_r[53], des_in_r[61],
                        des_in_r[03], des_in_r[11], des_in_r[19], des_in_r[27], des_in_r[35], des_in_r[43],
                        des_in_r[51], des_in_r[59], des_in_r[01], des_in_r[09], des_in_r[17], des_in_r[25],
                        des_in_r[33], des_in_r[41], des_in_r[49], des_in_r[57] };


// K schedule provides a linear means of intermixing the 56 bit K to form a
// different 48 bit K for each of the 16 bit rounds
DES_KEY_SEL U_DES_KEY_SEL(
                         .des_clk(des_clk),
                         .rst_n  (rst_n  ),
                         .K      (key_r  ),
                         .mode   (mode   ),
                         .K1     ( K1    ),
                         .K2     ( K2    ),
                         .K3     ( K3    ),
                         .K4     ( K4    ),
                         .K5     ( K5    ),
                         .K6     ( K6    ),
                         .K7     ( K7    ),
                         .K8     ( K8    ),
                         .K9     ( K9    ),
                         .K10    (K10    ),
                         .K11    (K11    ),
                         .K12    (K12    ),
                         .K13    (K13    ),
                         .K14    (K14    ),
                         .K15    (K15    ),
                         .K16    (K16    )
                         );

// 16 DES_CIPHER blocks 
DES_CIPHER U_DES_CIPHER1 ( .P(out0),  .R(IP[33:64]), .Ks(K1)  );
DES_CIPHER U_DES_CIPHER2 ( .P(out1),  .R(R0),        .Ks(K2)  );
DES_CIPHER U_DES_CIPHER3 ( .P(out2),  .R(R1),        .Ks(K3)  );
DES_CIPHER U_DES_CIPHER4 ( .P(out3),  .R(R2),        .Ks(K4)  );
DES_CIPHER U_DES_CIPHER5 ( .P(out4),  .R(R3),        .Ks(K5)  );
DES_CIPHER U_DES_CIPHER6 ( .P(out5),  .R(R4),        .Ks(K6)  );
DES_CIPHER U_DES_CIPHER7 ( .P(out6),  .R(R5),        .Ks(K7)  );
DES_CIPHER U_DES_CIPHER8 ( .P(out7),  .R(R6),        .Ks(K8)  );
DES_CIPHER U_DES_CIPHER9 ( .P(out8),  .R(R7),        .Ks(K9)  );
DES_CIPHER U_DES_CIPHER10( .P(out9),  .R(R8),        .Ks(K10) );
DES_CIPHER U_DES_CIPHER11( .P(out10), .R(R9),        .Ks(K11) );
DES_CIPHER U_DES_CIPHER12( .P(out11), .R(R10),       .Ks(K12) );
DES_CIPHER U_DES_CIPHER13( .P(out12), .R(R11),       .Ks(K13) );
DES_CIPHER U_DES_CIPHER14( .P(out13), .R(R12),       .Ks(K14) );
DES_CIPHER U_DES_CIPHER15( .P(out14), .R(R13),       .Ks(K15) );
DES_CIPHER U_DES_CIPHER16( .P(out15), .R(R14),       .Ks(K16) );

// 32 bit L0 get upper 32 bits of IP
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        L0 <= 32'b0;
    else
        L0 <= #1 IP[33:64];
end

// 32 bit R0 gets lower 32 bits of IP XOR'd with 32 bit out0
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        R0 <= 32'b0;
    else
        R0 <= #1  IP[01:32] ^ out0;
end

// 32 bit L1 gets 32 bit R0
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        L1 <= 32'b0;
    else
        L1 <= #1 R0;
end

// 32 bit R1 gets 32 bit L0 XOR'd with 32 bit out1
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        R1 <= 32'b0;
    else
        R1 <= #1 L0 ^ out1;
end

// 32 bit L2 gets 32 bit R1
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        L2 <= 32'b0;
    else
        L2 <= #1 R1;
end

// 32 bit R2 gets 32 bit L1 XOR'd with 32 bit out2
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        R2 <= 32'b0;
    else
        R2 <= #1 L1 ^ out2;
end
// 32 bit L3 get  32 bit R2
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        L3 <= 32'b0;
    else
        L3 <= #1 R2;
end

// 32 bit R3 gets 32 bit L2 XOR'd with 32 bit out3
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        R3 <= 32'b0;
    else
        R3 <= #1  L2 ^ out3;
end

// 32 bit L4 gets 32 bit R3
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        L4 <= 32'b0;
    else
        L4 <= #1 R3;
end

// 32 bit R4 gets 32 bit L3 XOR'd with 32 bit out4
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        R4 <= 32'b0;
    else
        R4 <= #1 L3 ^ out4;
end

// 32 bit L5 gets 32 bit R4
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        L5 <= 32'b0;
    else
        L5 <= #1 R4;
end

// 32 bit R5 gets 32 bit L4 XOR'd with 32 bit out5
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        R5 <= 32'b0;
    else
        R5 <= #1 L4 ^ out5;
end

// 32 bit L6 gets 32 bit R5
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        L6 <= 32'b0;
    else
        L6 <= #1 R5;
end

// 32 bit R6 gets 32 bit L5 XOR'd with 32 bit out6
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        R6 <= 32'b0;
    else
        R6 <= #1 L5 ^ out6;
end

// 32 bit L7 gets 32 bit R6
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        L7 <= 32'b0;
    else
        L7 <= #1 R6;
end

// 32 bit R7 gets 32 bit L6 XOR'd with 32 bit out7
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        R7 <= 32'b0;
    else
        R7 <= #1 L6 ^ out7;
end
// 32 bit L8 get  32 bit R7
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        L8 <= 32'b0;
    else
        L8 <= #1 R7;
end

// 32 bit R8 gets 32 bit L7 XOR'd with 32 bit out8
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        R8 <= 32'b0;
    else
        R8 <= #1  L7 ^ out8;
end

// 32 bit L9 gets 32 bit R8
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        L9 <= 32'b0;
    else
        L9 <= #1 R8;
end

// 32 bit R9 gets 32 bit L8 XOR'd with 32 bit out9
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        R9 <= 32'b0;
    else
        R9 <= #1 L8 ^ out9;
end

// 32 bit L10 gets 32 bit R9
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        L10 <= 32'b0;
    else
        L10 <= #1 R9;
end

// 32 bit R10 gets 32 bit L9 XOR'd with 32 bit out10
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        R10 <= 32'b0;
    else
        R10 <= #1 L9 ^ out10;
end

// 32 bit L11 gets 32 bit R10
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        L11 <= 32'b0;
    else
        L11 <= #1 R10;
end

// 32 bit R11 gets 32 bit L10 XOR'd with 32 bit out11
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        R11 <= 32'b0;
    else
        R11 <= #1 L10 ^ out11;
end

// 32 bit L12 gets 32 bit R11
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        L12 <= 32'b0;
    else
        L12 <= #1 R11;
end

// 32 bit R12 gets 32 bit L11 XOR'd with 32 bit out12
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        R12 <= 32'b0;
    else
        R12 <= #1 L11 ^ out12;
end

// 32 bit L13 gets 32 bit R12
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        L13 <= 32'b0;
    else
        L13 <= #1 R12;
end
// 32 bit R13 gets 32 bit L12 XOR'd with 32 bit out13
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        R13 <= 32'b0;
    else
        R13 <= #1 L12 ^ out13;
end

// 32 bit L14 gets 32 bit R13
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        L14 <= 32'b0;
    else
        L14 <= #1 R13;
end

// 32 bit R12 gets 32 bit L11 XOR'd with 32 bit out12
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        R14 <= 32'b0;
    else
        R14 <= #1 L13 ^ out14;
end

// 32 bit L15 gets 32 bit R14
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        L15 <= 32'b0;
    else
        L15 <= #1 R14;
end

// 32 bit R15 gets 32 bit L14 XOR'd with 32 bit out15
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n==1'b0)
        R15 <= 32'b0;
    else
        R15 <= #1 L14 ^ out15;
end


// XOR 32 bit out15 with 32 bit L14      ( FP  1:32 )
// then concatinate the 32 bit R14 value ( FP 33:64 )
// This value ( FP 1:64 ) is then registered by the des_out[63:0] register 
//assign FP = { (out15 ^ L14), R14};
assign FP = { (out15 ^ L14), R14};

// Perform the final permutation
always @(posedge des_clk or negedge rst_n)
begin
    if(rst_n == 1'b0)
        des_out <= 64'b0;
    else
        des_out <= #1 {  FP[40], FP[08], FP[48], FP[16], FP[56], FP[24], FP[64], FP[32], 
                         FP[39], FP[07], FP[47], FP[15], FP[55], FP[23], FP[63], FP[31], 
                         FP[38], FP[06], FP[46], FP[14], FP[54], FP[22], FP[62], FP[30], 
                         FP[37], FP[05], FP[45], FP[13], FP[53], FP[21], FP[61], FP[29], 
                         FP[36], FP[04], FP[44], FP[12], FP[52], FP[20], FP[60], FP[28], 
                         FP[35], FP[03], FP[43], FP[11], FP[51], FP[19], FP[59], FP[27],
                         FP[34], FP[02], FP[42], FP[10], FP[50], FP[18], FP[58], FP[26], 
                         FP[33], FP[01], FP[41], FP[09], FP[49], FP[17], FP[57], FP[25] };
end

endmodule