fincount.vhd

基于FPGA的频率计模块设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FinCount is
port(st:in std_logic;
     fout:out std_logic_vector(24 downto 0);
     --pout:out std_logic_vector(24 downto 0);
     --fin2:in std_logic;
     clk,fin1:in std_logic;
     done:out std_logic
      );
end FinCount;
architecture rtl of FinCount is
signal buff1:std_logic_vector(19 downto 0);
signal count1:std_logic_vector(24 downto 0);
--signal count2:std_logic_vector(17 downto 0);
--signal en2:std_logic;
signal en1,rs:std_logic;
begin

first:process(st,fin1,clk)--计数开始标志
begin
  if  (fin1'event and fin1='1') then
     if st='1' then 
       if buff1="00000000000000010000" then buff1<="00000000000000000000"; 
       else buff1<=buff1+1;    --当时钟信号clk变化时 
       end if;
     else buff1<="00000000000000000000";
end if; 
end if;

end process first;


inter1:process(buff1)
begin
  if buff1="00000000000000000000" then
           en1<='0';rs<='0';done<='1';
     elsif buff1="00000000000000000001" then
             en1<='0';rs<='1';done<='1';
     elsif buff1<"00000000000000000101" then
             en1<='0';done<='0';
     elsif buff1<"00000000000000001101" then             
             en1<='1';rs<='0';done<='0';

     elsif buff1<"00000000000000010000" then
            en1<='0';rs<='0';done<='1';
   else          en1<='0';done<='1';
  end if;
end process inter1;



count1n:process(clk,rs)--计数（频率）
begin
if rs='1' then
    count1<=(others=>'0');
  elsif  (clk'event and clk='1') then
     if st='1' then 
         if en1='1' then
           count1<=count1+1;
           --show<=(fin2 AND (NOT fin1));               --判断纤维超前的标志
         else fout<=count1;
         end if;
     end if;
  end if;
end process count1n;


--inter2:process(clk)
--begin
  --if en1='1' then 
     --en2<=fin1 xor fin2;
  --else en2<='0';
  --end if;
--end process inter2;

--count2n:process(clk,rs)--计数（相位）
--begin
--if rs='1' then
  --  count2<=(others=>'0');pout<=(others=>'0');
  --elsif  (clk'event and clk='1') then
  --   if st='1' then 
  --       if en2='1' then
  --         count2<=count2+1;
  --       else pout<=count2;
  --       end if;
  --   end if;
--  end if;
--end process count2n;

end rtl;