ad.vhd

tlc0820 vhdl 程序,控制ad的采集数据

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_ARITH.all;
use IEEE.std_logic_UNSIGNED.all;
entity AD is
	port (
		--以下是引脚信号
		
		CLK       :IN	STD_LOGIC;  --系统时钟
		RST_N     :IN	STD_LOGIC;  --系统复位
		--AD0809部分接口
		AD_INT    :IN	STD_LOGIC;	--中断信号,转换完毕即中断,电平中断
		AD_CS     :OUT	STD_LOGIC;	--片选信号
		AD_RD     :OUT	STD_LOGIC;	--写信号
		AD_WR     :INOUT	STD_LOGIC;	--读信号
		AD_D	  :IN   STD_LOGIC_VECTOR(7 downto 0); --8位采集数据
        AD_Q	  :out  STD_LOGIC_VECTOR(7 downto 0) --8位输出数据
		);
end AD;

ARCHITECTURE behav OF AD IS

type statetype is(AD_IDLE, AD_WRITE, AD_WAIT, AD_WAIT1, AD_READ, AD_READ1, AD_STOP);
signal present_state,next_state: statetype;
signal datain: STD_LOGIC_VECTOR(7 downto 0);		

BEGIN

--AD控制状态机
P1: process(present_state,next_state,AD_INT)
 begin
   case present_state is
     when AD_IDLE => 
		AD_CS <= '1';  
		AD_RD <= '1';
		AD_WR <= '1';
        next_state <= AD_WRITE;
     when AD_WRITE => 			--写信号
		AD_CS <= '0';
		AD_WR <= '0';
		AD_RD <= '1';
        next_state <= AD_WAIT;
     when AD_WAIT => 			--写结束
		AD_CS <= '0';AD_WR <= '1';AD_RD <= '1';
	    if (AD_INT = '0') then	--当由1变0时,转换结束
	    	next_state <= AD_WAIT1;
		else
			next_state <= AD_WAIT;
        end if;
	 when AD_WAIT1 => 
	     AD_CS <= '0';
		 AD_WR <= '1';
		 AD_RD <= '0';
	    	next_state <= AD_READ;
		
     when AD_READ => 			--写信号 
		AD_CS <= '0';
		AD_WR <= '1';
		AD_RD <= '0';
		    next_state <= AD_READ1;
	 when AD_READ1 =>			--读锁存
		AD_CS <= '0';
		AD_WR <= '1';
		AD_RD <= '1';
        next_state <= AD_STOP;
	 when AD_STOP =>
        AD_CS <= '1';
		AD_WR <= '1';
		AD_RD <= '1';
		 next_state <= AD_IDLE;
     end case;
end process P1;

P2: process(CLK, RST_N)
 begin
   if (RST_N = '0') then
     present_state <= AD_IDLE;
     datain <= "00000000";
   elsif falling_edge(CLK) then
     present_state <= next_state;
     if(present_state = AD_READ) then
       datain <= AD_D;
     end if;
   end if;
AD_Q<=datain;
end process P2;
END behav;