f220fullc.dat

Templates for c51 from Cygnal

1TITLEWatchdog Timer Configuration
 2Select Timeout Interval
  3Timeout Interval: 1048576 x Tsysclk[FF=07,FF]D
  3Timeout Interval:  262144 x Tsysclk[FF=06,FF] 
  3Timeout Interval:   65636 x Tsysclk[FF=05,FF] 
  3Timeout Interval:   16384 x Tsysclk[FF=04,FF] 
  3Timeout Interval:    4096 x Tsysclk[FF=03,FF] 
  3Timeout Interval:    1024 x Tsysclk[FF=02,FF] 
  3Timeout Interval:     256 x Tsysclk[FF=01,FF] 
  3Timeout Interval:      64 x Tsysclk[FF=00,FF] 
 2WDT Controls 
  3Disable WDT[FF=00,00]{NX}@08
  3Disable WDT Lockout[FF=00,00]{NX}@64
  3Enable/Reset WDT[FF=00,00]{NX}@94
1Port I/0 MUX
 2TITLEConfigure the PRTnMX Registers
  3Select Peripherals to Enable
   4UART Enable[E1=01,01]{NX}@65B
   4/INT0 Enable[E1=04,04]{NX}@65B
   4/INT1 Enable[E1=08,08]{NX}@65B
   4T0 Enable[E1=10,10]{NX}@65B   
   4T1 Enable[E1=20,20]{NX}@65B
   4T2 Enable[E1=40,40]{NX}@65B
   4T2EX Enable[E1=80,80]{NX}@65B
   4CP0 Enable[E2=01,01]{NX}@65B
   4CP1 Enable[E2=02,02]{NX}@65B  
   4SYSCLK Enable[E2=40,40]{NX}@65B
   4SPI Bus Enable[E3=01,01]{NX}@65B
2TITLESelect Pin I/0
 3Port Pin Pull-Up Selection
  4Weak Pull-Ups globally disabled[E3=80,80]
  4Port 0 Weak Pull-Ups Disabled[E3=08,08]
  4Port 1 Weak Pull-Ups Disabled[E3=10,10]
  4Port 2 Weak Pull-Ups Disabled[E3=20,20]
  4Port 3 Weak Pull-Ups Disabled[E3=40,40]
 3Port Pin Output Mode
  4Port 0 Configure
   5Bit 0 of Port 0 Push Pull Output[A4=01,01]{NX}@67
   5Bit 1 of Port 0 Push Pull Output[A4=02,02]{NX}@67
   5Bit 2 of Port 0 Push Pull Output[A4=04,04]{NX}@67
   5Bit 3 of Port 0 Push Pull Output[A4=08,08]{NX}@67
   5Bit 4 of Port 0 Push Pull Output[A4=10,10]{NX}@67
   5Bit 5 of Port 0 Push Pull Output[A4=20,20]{NX}@67
   5Bit 6 of Port 0 Push Pull Output[A4=40,40]{NX}@67
   5Bit 7 of Port 0 Push Pull Output[A4=80,80]{NX}@67
  4Port 1 Configure
   5Bit 0 of Port 1 Push Pull Output[A5=01,01]{NX}@67
   5Bit 1 of Port 1 Push Pull Output[A5=02,02]{NX}@67
   5Bit 2 of Port 1 Push Pull Output[A5=04,04]{NX}@67
   5Bit 3 of Port 1 Push Pull Output[A5=08,08]{NX}@67
   5Bit 4 of Port 1 Push Pull Output[A5=10,10]{NX}@67
   5Bit 5 of Port 1 Push Pull Output[A5=20,20]{NX}@67
   5Bit 6 of Port 1 Push Pull Output[A5=40,40]{NX}@67
   5Bit 7 of Port 1 Push Pull Output[A5=80,80]{NX}@67
  4Port 2 Configure
   5Bit 0 of Port 2 Push Pull Output[A6=01,01]{NX}@67
   5Bit 1 of Port 2 Push Pull Output[A6=02,02]{NX}@67
   5Bit 2 of Port 2 Push Pull Output[A6=04,04]{NX}@67
   5Bit 3 of Port 2 Push Pull Output[A6=08,08]{NX}@67
   5Bit 4 of Port 2 Push Pull Output[A6=10,10]{NX}@67
   5Bit 5 of Port 2 Push Pull Output[A6=20,20]{NX}@67
   5Bit 6 of Port 2 Push Pull Output[A6=40,40]{NX}@67
   5Bit 7 of Port 2 Push Pull Output[A6=80,80]{NX}@67
  4Port 3 Configure 
   5Bit 0 of Port 3 Push Pull Output[A7=01,01]{NX}@67
   5Bit 1 of Port 3 Push Pull Output[A7=02,02]{NX}@67
   5Bit 2 of Port 3 Push Pull Output[A7=04,04]{NX}@67
   5Bit 3 of Port 3 Push Pull Output[A7=08,08]{NX}@67
   5Bit 4 of Port 3 Push Pull Output[A7=10,10]{NX}@67
   5Bit 5 of Port 3 Push Pull Output[A7=20,20]{NX}@67
   5Bit 6 of Port 3 Push Pull Output[A7=40,40]{NX}@67
   5Bit 7 of Port 3 Push Pull Output[A7=80,80]{NX}@67
  3Port Pin Input Mode
   4Port 0
	  5Bit 0 of Port 0 Analog[F1=00,01]{NX}@97
      5Bit 1 of Port 0 Analog[F1=00,02]{NX}@97
	  5Bit 2 of Port 0 Analog[F1=00,04]{NX}@97
	  5Bit 3 of Port 0 Analog[F1=00,08]{NX}@97
	  5Bit 4 of Port 0 Analog[F1=00,10]{NX}@97
      5Bit 5 of Port 0 Analog[F1=00,20]{NX}@97
	  5Bit 6 of Port 0 Analog[F1=00,40]{NX}@97
	  5Bit 7 of Port 0 Analog[F1=00,80]{NX}@97
	 4Port 1
	  5Bit 0 of Port 1 Analog[F2=00,01]{NX}@97
	  5Bit 1 of Port 1 Analog[F2=00,02]{NX}@97
	  5Bit 2 of Port 1 Analog[F2=00,04]{NX}@97
	  5Bit 3 of Port 1 Analog[F2=00,08]{NX}@97
	  5Bit 4 of Port 1 Analog[F2=00,10]{NX}@97
      5Bit 5 of Port 1 Analog[F2=00,20]{NX}@97
	  5Bit 6 of Port 1 Analog[F2=00,40]{NX}@97
	  5Bit 7 of Port 1 Analog[F2=00,80]{NX}@97
     4Port 2
	  5Bit 0 of Port 2 Analog[F3=00,01]{NX}@97
	  5Bit 1 of Port 2 Analog[F3=00,02]{NX}@97
	  5Bit 2 of Port 2 Analog[F3=00,04]{NX}@97
	  5Bit 3 of Port 2 Analog[F3=00,08]{NX}@97
	  5Bit 4 of Port 2 Analog[F3=00,10]{NX}@97
      5Bit 5 of Port 2 Analog[F3=00,20]{NX}@97
	  5Bit 6 of Port 2 Analog[F3=00,40]{NX}@97
	  5Bit 7 of Port 2 Analog[F3=00,80]{NX}@97
     4Port 3
	  5Bit 0 of Port 3 Analog[F4=00,01]{NX}@97
	  5Bit 1 of Port 3 Analog[F4=00,02]{NX}@97
	  5Bit 2 of Port 3 Analog[F4=00,04]{NX}@97
	  5Bit 3 of Port 3 Analog[F4=00,08]{NX}@97
	  5Bit 4 of Port 3 Analog[F4=00,10]{NX}@97
      5Bit 5 of Port 3 Analog[F4=00,20]{NX}@97
	  5Bit 6 of Port 3 Analog[F4=00,40]{NX}@97
	  5Bit 7 of Port 3 Analog[F4=00,80]{NX}@97
 2TITLEView port pinout
1TITLEComparators
 2Comparator 0
   3Initially Enabled? [9E=80,80]{NX}@16
   3Positive hysterisis?
    4Disabled [9E=00,0C]D
	4'4.5mV'  [9E=04,0C]
	4'9mV' [9E=08,0C]
	4'17mV' [9E=0C,0C]
   3Negative hysterisis?
    4Disabled [9E=00,03]D
	4'4.5mV'  [9E=01,03]
	4'9mV' [9E=02,03]
	4'17mV' [9E=03,03]
   3Comp0 Rising Edge Interrupt Enabled?[E6=20,20]{NX}@15
    4Comparator 0 Rising Edge Interrupt Priority High?[F6=20,20]@15
   3Comp0 Falling Edge Interrupt Enabled?[E6=10,10]{NX}@15
    4Comparator 0 Falling Edge Interrupt Priority High?[F6=10,10]@15
   3Enable Comparator 0 as Reset Source?[EF=20,20]{NX}@05
 2Comparator 1
  3Initially Enabled?[9F=80,80]{NX}@17
  3Positive hysterisis?
    4Disabled [9F=00,0C]D
	4'4.5mV'  [9F=04,0C]
	4'9mV' [9F=08,0C]
	4'17mV' [9F=0C,0C]
  3Negative hysterisis?
    4Disabled [9F=00,03]D
	4'4.5mV'  [9F=01,03]
	4'9mV' [9F=02,03]
	4'17mV' [9F=03,03]
  3Comp1 Rising Edge Interrupt Enabled?[E6=80,80]@15
   4Comparator 1 Rising Edge Interrupt Priority High?[F6=80,80]@15
  3Comp1 Falling Edge Interrupt Enabled?[E6=40,40]@15
   4Comparator 1 Falling Edge Interrupt Priority High?[F6=40,40]@15
1TITLEOscillator Configuration
 2Internal Oscillator
  3Enable Internal Oscillator?[B2=04,04]D{NX}@70
  3Select Internal Oscillator typical Frequency Note: Frequency Varies 20%
   4'2MHz'[B2=00,03]D@0C 
   4'4MHz'[B2=01,03]@0D
   4'8MHz'[B2=02,03]@0E
   4'16MHz'[B2=03,03]@0F
 2External Oscillator
  3Select External Oscillator Mode to Enable
   4Off. XTAL1 pin is grounded internally[B1=00,60]@09
   4CMOS Clock on XTAL1 pin Note: XTAL1 is NOT 5V tolerant[B1=20,70]@09
   4CMOS Clock on XTAL1 pin with divide by 2 Stage Note: XTAL1 is NOT 5V tolerant[B1=30,70]D@09
   5Select Frequency
    5'f<=25KHz'[B1=00,07]D@68
    5'25KHz<f<=50KHz'[B1=01,07]@68
    5'50KHz<f<=100KHz'[B1=02,07]@68
    5'100KHz<f<=200KHz'[B1=03,07]@68
    5'200KHz<f<=400KHz'[B1=04,07]@68
    5'400KHz<f<=800KHz'[B1=05,07]@68
    5'800KHz<f<=1.6MHz'[B1=06,07]@68
    5'1.6MHz<f<=3.2MHz'[B1=07,07]@68
   4C Oscillator Mode with divide by 2 stage Note: frequency is inversely proportional with capacitance for C=100pF frequency is 1/3 of 33pFfor C=100pF frequency is 1/3 of 33pF[B1=40,70]@09
    5Select Frequency Assuming C=33pF and AV+=3.3V
    5'4.04KHz'[B1=00,07]D@69
    5'12.9KHz'[B1=01,07]@69
    5'40.40KHz'[B1=02,07]@69
    5'119KHz'[B1=03,07]@69
    5'349KHz'[B1=04,07]@69
    5'918KHz'[B1=05,07]@69
    5'3.86MHz'[B1=06,07]@69
    5'12.9MHz'[B1=07,07]@69
   4Crystal Oscillator Mode[B1=60,70]@09
    5Select Frequency
    5'f<=12.5kHz[B1=00,07]D@6A
    5'12.5kHz<f<=30.3kHz'[B1=01,07]@6A
    5'30.35Hz<f<=93.8kHz'[B1=02,07]@6A
    5'93.8kHz<f<=267kHz'[B1=03,07]@6A
    5'267kHz<f<=722kHz'[B1=04,07]@6A
    5'722kHz<f<=2.23MHz'[B1=05,07]@6A
    5'2.23MHz<f<=6.74MHz'[B1=06,07]@6A
    5'f>=6.74MHz'[B1=07,07]@6A
   4Crystal Oscillator Mode with divide by 2 stage[B1=70,70]@09
    5Select Frequency
    5'f<=12.5kHz[B1=00,07]D@6B
    5'12.5kHz<f<=30.3kHz'[B1=01,07]@6B
    5'30.35Hz<f<=93.8kHz'[B1=02,07]@6B
    5'93.8kHz<f<=267kHz'[B1=03,07]@6B
    5'267kHz<f<=722kHz'[B1=04,07]@6B
    5'722kHz<f<=2.23MHz'[B1=05,07]@6B
    5'2.23MHz<f<=6.74MHz'[B1=06,07]@6B
    5'f>=6.74MHz'[B1=07,07]@6B
 2Select SYSCLK Source
  3Internal Oscillator?[B2=00,08]D
  3External Oscillator?[B2=08,08]@63
 2Missing Clock Detector
  3Enable Missing Clock Detector?[B2=80,80]