f002full.dat

Templates for c51 from Cygnal

1TITLEWatchdog Timer Configuration
 2Select Timeout Interval
  3Timeout Interval: 1048576 x Tsysclk[FF=07,FF]D
  3Timeout Interval:  262144 x Tsysclk[FF=06,FF] 
  3Timeout Interval:   65636 x Tsysclk[FF=05,FF] 
  3Timeout Interval:   16384 x Tsysclk[FF=04,FF] 
  3Timeout Interval:    4096 x Tsysclk[FF=03,FF] 
  3Timeout Interval:    1024 x Tsysclk[FF=02,FF] 
  3Timeout Interval:     256 x Tsysclk[FF=01,FF] 
  3Timeout Interval:      64 x Tsysclk[FF=00,FF] 
 2WDT Controls 
  3Disable WDT[FF=00,00]{NX}@08
  3Disable WDT Lockout[FF=00,00]{NX}@64
  3Enable/Reset WDT[FF=00,00]{NX}@94
1Port I/0 Crossbar
2TITLEConfigure the XBRn Registers
  3Select Peripherals to Enable
   4SMBus Enabled?[E1=01,01]{NX}@5B
   4SPI Bus Enable?[E1=02,02]{NX}@5B
   4UART Enabled[E1=04,04]{NX}@5B
   4PCA
	5ECIE:PCA0 Counter Enabled?[E1=40,40]{NX}@5B
     6Enable CEX0,CEX1,CEX2,CEX3,CEX4[E1=28,38]@71
     6Enable CEX0,CEX1,CEX2,CEX3[E1=20,38]@71
     6Enable CEX0,CEX1,CEX2[E1=18,38]@71
     6Enable CEX0,CEX1[E1=10,38]@71
     6Enable CEX0[E1=08,38]@71
     6Disable PCA I/O[E1=00,38]D@71
   4Comparator 0 Enabled?[E1=80,80]{NX}@5B
   4Timer 0 Enable?[E2=02,02]{NX}@5B
   4/INT0 Enabled?[E2=04,04]{NX}@5B
   4Timer 1 Enabled?[E2=08,08]{NX}@5B
   4/INT1 Enabled?[E2=10,10]{NX}@5B 
   4Timer 2 Enabled?[E2=20,20]{NX}@5B
   4T2EX Enabled?[E2=40,40]{NX}@5B
   4SYSCLK Enabled?[E2=80,80]{NX}@5B
   4CNVSTR Enable[E3=01,01]{NX}@5B
2TITLESelect Pin I/0
 3Port Pin Pull-Up Selection
  4Weak Pull-Ups globally disabled[E3=80,80]
  4Port 0 Weak Pull-Ups Disabled[E3=08,08]
 3Port Pin Output Mode
  4Port 0 Configure
   5Bit 0 of Port 0 Push Pull Output[A4=01,01]{NX}@67
   5Bit 1 of Port 0 Push Pull Output[A4=02,02]{NX}@67
   5Bit 2 of Port 0 Push Pull Output[A4=04,04]{NX}@67
   5Bit 3 of Port 0 Push Pull Output[A4=08,08]{NX}@67
   5Bit 4 of Port 0 Push Pull Output[A4=10,10]{NX}@67
   5Bit 5 of Port 0 Push Pull Output[A4=20,20]{NX}@67
   5Bit 6 of Port 0 Push Pull Output[A4=40,40]{NX}@67
   5Bit 7 of Port 0 Push Pull Output[A4=80,80]{NX}@67
 2TITLEView port pinout
1TITLEComparators
 2Comparator 0
   3Enable Comparator 0 Output on the Port I/O Cross Bar?[E1=80,80]{NX}@5B
   3Initially Enabled? [9E=80,80]{NX}@16
   3Positive hysterisis?
    4Disabled [9E=00,0C]D
	4'5mV'  [9E=04,0C]
	4'10mV' [9E=08,0C]
	4'20mV' [9E=0C,0C]
   3Negative hysterisis?
    4Disabled [9E=00,03]D
	4'5mV'  [9E=01,03]
	4'10mV' [9E=02,03]
	4'20mV' [9E=03,03]
   3Comp0 Rising Edge Interrupt Enabled?[E6=20,20]{NX}@15
    4Comparator 0 Rising Edge Interrupt Priority High?[F6=20,20]@15
   3Comp0 Falling Edge Interrupt Enabled?[E6=10,10]{NX}@15
    4Comparator 0 Falling Edge Interrupt Priority High?[F6=10,10]@15
   3Enable Comparator 0 as Reset Source?[EF=20,20]{NX}@05
1TITLEOscillator Configuration
 2Enable SYSCLK Output on the Port I/O Cross Bar?[E2=80,80]{NX}@5B
 2Internal Oscillator
  3Enable Internal Oscillator?[B2=04,04]D{NX}@70
  3Select Internal Oscillator typical Frequency Note: Frequency Varies 20%
   4'2MHz'[B2=00,03]D@0C 
   4'4MHz'[B2=01,03]@0D
   4'8MHz'[B2=02,03]@0E
   4'16MHz'[B2=03,03]@0F
 2External Oscillator
  3Select External Oscillator Mode to Enable
   4Off. XTAL1 pin is grounded internally[B1=00,60]@09
   4CMOS Clock on XTAL1 pin Note: XTAL1 is NOT 5V tolerant[B1=20,70]@09
   4CMOS Clock on XTAL1 pin with divide by 2 Stage Note: XTAL1 is NOT 5V tolerant[B1=30,70]D@09
   4RC Oscillator Mode with divide by 2 stage[B1=40,70]@09
    5Select Frequency
    5'f<=25KHz'[B1=00,07]D@68
    5'25KHz<f<=50KHz'[B1=01,07]@68
    5'50KHz<f<=100KHz'[B1=02,07]@68
    5'100KHz<f<=200KHz'[B1=03,07]@68
    5'200KHz<f<=400KHz'[B1=04,07]@68
    5'400KHz<f<=800KHz'[B1=05,07]@68
    5'800KHz<f<=1.6MHz'[B1=06,07]@68
    5'1.6MHz<f<=3.2MHz'[B1=07,07]@68
   4C Oscillator Mode with divide by 2 stage Note: frequency is inversely proportional with capacitance for C=100pF frequency is 1/3 of 33pFfor C=100pF frequency is 1/3 of 33pF[B1=40,70]@09
    5Select Frequency Assuming C=33pF and AV+=3.3V
    5'4.04KHz'[B1=00,07]D@69
    5'12.9KHz'[B1=01,07]@69
    5'40.40KHz'[B1=02,07]@69
    5'119KHz'[B1=03,07]@69
    5'349KHz'[B1=04,07]@69
    5'918KHz'[B1=05,07]@69
    5'3.86MHz'[B1=06,07]@69
    5'12.9MHz'[B1=07,07]@69
   4Crystal Oscillator Mode[B1=60,70]@09
    5Select Frequency
    5'f<=12.5kHz[B1=00,07]D@6A
    5'12.5kHz<f<=30.3kHz'[B1=01,07]@6A
    5'30.35Hz<f<=93.8kHz'[B1=02,07]@6A
    5'93.8kHz<f<=267kHz'[B1=03,07]@6A
    5'267kHz<f<=722kHz'[B1=04,07]@6A
    5'722kHz<f<=2.23MHz'[B1=05,07]@6A
    5'2.23MHz<f<=6.74MHz'[B1=06,07]@6A
    5'f<=6.74MHz'[B1=07,07]@6A
   4Crystal Oscillator Mode with divide by 2 stage[B1=70,70]@09
    5Select Frequency
    5'f<=12.5kHz[B1=00,07]D@6B
    5'12.5kHz<f<=30.3kHz'[B1=01,07]@6B
    5'30.35Hz<f<=93.8kHz'[B1=02,07]@6B
    5'93.8kHz<f<=267kHz'[B1=03,07]@6B
    5'267kHz<f<=722kHz'[B1=04,07]@6B
    5'722kHz<f<=2.23MHz'[B1=05,07]@6B
    5'2.23MHz<f<=6.74MHz'[B1=06,07]@6B
    5'f<=6.74MHz'[B1=07,07]@6B
 2Select SYSCLK Source
  3Internal Oscillator?[B2=00,08]D{NX}@93
  3Enable Missing Clock Detector?[B2=80,80]{NX}
1TITLEReference Control Register
 2Temperature Sensor Enabled?[D1=04,04]{NX}
 2Reference Buffer Control
  3Internal VREF[D1=01,01]@5E
 2Enable Internal Bias Generator?[D1=02,02]{NX}
1TITLESPI Configuration
 2SPI Interrupt Enabled?[E6=01,01]{NX}@15
  3Set SPI Interrupt Priority High?[F6=01,01]@15
 2Enable SPI Bus I/O on the Port I/O Crossbar?[E1=02,02]{NX}@5B
 2SPI Clock Phase
  3Data sampled on first edge of SCK?[9A=00,80]D
  3Data sampled on second edge of SCK?[9A=80,80]
 2SPI Clock Polarity
  3SCK data sampled on rising edge?[9A=00,40]D
  3SCK data sampled on falling edge?[9A=40,40]
 2Select Mode
  3Enable Master Mode?[F8=02,02]@6C
   4SPI Frame Size
    5'1'[9A=00,07]D@6D
    5'2'[9A=01,07]@6D
    5'3'[9A=02,07]@6D
    5'4'[9A=03,07]@6D
    5'5'[9A=04,07]@6D
    5'6'[9A=05,07]@6D
    5'7'[9A=06,07]@6D
    5'8'[9A=07,07]@6D
   4SPI Clock Frequency
    5Frequency=SYSCLK/2[9A=00,00]@10	  
    5Frequency=SYSCLK/10[9A=00,00]@11
    5Frequency=SYSCLK/200[9A=00,00]@12
    5Click to Set Custom Frequency[9A=00,00]@13
  3Enable Slave Mode?[F8=00,02]D@6C
 2Enable SPI?[F8=00,00]{NX}@14
1TITLEDAC Configuration
 2DAC0
  3Enable DAC0?[D4=80,80]{NX}@07
  3Data Format					     DAC0H	  DAC0L
   4Use DAC0H:DAC0L[11:0] (MSB=DAC0H.3)   0000 dddd	dddd dddd[D4=00,07]D@5F
   4Use DAC0H:DAC0L[12:1] (MSB=DAC0H.4)   000d dddd	dddd ddd0[D4=01,07]@5F
   4Use DAC0H:DAC0L[13:2] (MSB=DAC0H.5)   00dd dddd	dddd dd00[D4=02,07]@5F
   4Use DAC0H:DAC0L[14:3] (MSB=DAC0H.6)   0ddd dddd	dddd d000[D4=03,07]@5F
   4Use DAC0H:DAC0L[15:4] (MSB=DAC0H.7)   dddd dddd	dddd 0000[D4=04,07]@5F 
 2DAC1
  3Enable DAC1?[D7=80,80]{NX}@07
  3Data Format					     DAC0H	  DAC0L
   4Use DAC1H:DAC1L[11:0] (MSB=DAC0H.3)   0000 dddd	dddd dddd[D7=00,07]D@60
   4Use DAC1H:DAC1L[12:1] (MSB=DAC0H.4)   000d dddd	dddd ddd0[D7=01,07]@60
   4Use DAC1H:DAC1L[13:2] (MSB=DAC0H.5)   00dd dddd	dddd dd00[D7=02,07]@60
   4Use DAC1H:DAC1L[14:3] (MSB=DAC0H.6)   0ddd dddd	dddd d000[D7=03,07]@60
   4Use DAC1H:DAC1L[15:4] (MSB=DAC0H.7)   dddd dddd	dddd 0000[D7=04,07]@60
1TITLEUART Configuration
 2UART Interrupt Configuration
  3Clear UART Recieve and Transmit Interrupt Flags(RECOMMENDED)?[98=00,00]{NX}@28 
  3Enable Serial Port (UART) Interrupt?[A8=10,10]{NX}@29
   4Set Serial Port (UART) Interrupt Priority High?[B8=10,10]@29
 2Enable UART I/O on the Port I/O Crossbar?[E1=04,04]{NX}@5B
   2Enable UART Reception?[98=10,10]{NX}
 2Select UART Mode
  3 0: Synchronous Mode: Baud Rate=SYSCLK/12[98=00,C0]@6E
  3 1: Asynchronous Mode: 8-bit UART, Variable Baud Rate[98=40,C0]@6E
   4Use Timer 1 as Baud Rate Source?[88=40,40]@19
    5Enable Serial Port Baud Rate Doubler(SMOD=1)?[87=80,80]{NX}
    5Timer 1 uses the system clock not divided by 12(T1M=1)[8E=10,10]{NX}@19
    5Click to set 8-bit TH1 reload value[8E=00,00]{NX}@18
   4Use Timer 2 as Baud Rate Source?[C8=34,34]@27
    5Custom RCLK and TCLK settings
     6Use Timer 2 overflows for Transmit Clock?[C8=10,10]{NX}@62
     6Use Timer 2 overflows for Receive Clock?[C8=20,20]{NX}@62
    5Click to set 16-bit RCAP2H:RCAP2L reload value[8E=00,00]{NX}@20
  3 2: Asynchronous Mode: 9-bit UART, Fixed Baud Rate[98=80,C0]@6E
   4SYSCLK/32?[87=80,80]
   4SYSCLK/64?[87=00,80]D
  3 3: Asychronous Mode: 9-bit UART,Variable Baud Rate[98=C0,C0]@6E
   4Use Timer 1 as Baud Rate Source?[88=40,40]{NX}D@19
    5Enable Serial Port Baud Rate Doubler(SMOD=1)?[87=80,80]{NX}
    5Timer 1 uses system clock not divided by 12(T1M=0)[8E=10,10]{NX}@19
    5Click to set 8-bit TH1 reload value[8E=00,00]{NX}@18
   4Use Timer 2 as Baud Rate Source?[C8=34,34]@27
    5Custom RCLK and TCLK settings
     6Timer 2 overflows used for Transmit Clock?[C8=10,10]{NX}
     6Timer 2 overflows used for Receive Clock?[C8=20,20]{NX}
    5Click to set 16-bit RCAP2H:RCAP2L reload value[8E=00,00]{NX}@20
1TITLESMBus Configuration
 2Enable?[C0=40,40]
  3Enable SMBus Interrupt?[E6=02,02]{NX}@15
   4Set SMBus Interrupt Priority High?[F6=02,02]@15
  3Enable SMBus Bus I/O on the Port I/O Crossbar?[E1=01,01]{NX}@5B
  3Enable Slave Mode?[C0=04,04]{NX}
   4Respond to General Call Address[C3=01,01]
   4Click to enter 7-bit Slave Address@2A
  3SCL low timeout enabled?[C0=01,01]{NX}
  3SCL high timeout enabled?[C0=02,02]{NX}
  3Set SMB0CR SMBus Clock Rate Register
   4Click to set SMBus Clock Rate[CF=00,00]@2B
1TITLEPCA Configuration
 2Enable PCA Module I/O on the Port I/O Crossbar?
  3Enable CEX0,CEX1,CEX2,CEX3,CEX4 on the Port I/O Crossbar[E1=28,38]@5B
  3Enable CEX0,CEX1,CEX2,CEX3 on the Port I/O Crossbar[E1=20,38]@5B
  3Enable CEX0,CEX1,CEX2 on the Port I/O Crossbar[E1=18,38]@5B
  3Enable CEX0,CEX1 on the Port I/O Crossbar[E1=10,38]@5B
  3Enable CEX0 on the Port I/O Crossbar[E1=08,38]@5B
  3Disable Module I/O[E1=00,38]D@5B
 2Enable PCA Counter Input on the Port I/O Crossbar?[E1=40,40]{NX}@5B
 2Enable PCA Interrupt?[E6=08,08]{NX}@15
  3Set PCA Interrupt Priority High?[F6=08,08]@15
 2Timer/Counter
  3Clock Source
   4SYSCLK/12[D9=00,06]D
   4SYSCLK/4[D9=02,06]
   4Timer 0 overflow[D9=04,06]
   4High-to-low transitions on ECI(max rate = SYSCLK/4)[D9=06,06]