📄 f230fullc.dat
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1TITLEWatchdog Timer Configuration
2Select Timeout Interval
3Timeout Interval: 1048576 x Tsysclk[FF=07,FF]D
3Timeout Interval: 262144 x Tsysclk[FF=06,FF]
3Timeout Interval: 65636 x Tsysclk[FF=05,FF]
3Timeout Interval: 16384 x Tsysclk[FF=04,FF]
3Timeout Interval: 4096 x Tsysclk[FF=03,FF]
3Timeout Interval: 1024 x Tsysclk[FF=02,FF]
3Timeout Interval: 256 x Tsysclk[FF=01,FF]
3Timeout Interval: 64 x Tsysclk[FF=00,FF]
2WDT Controls
3Disable WDT[FF=00,00]{NX}@08
3Disable WDT Lockout[FF=00,00]{NX}@64
3Enable/Reset WDT[FF=00,00]{NX}@94
1Port I/0 MUX
2TITLEConfigure the PRTnMX Registers
3Select Peripherals to Enable
4UART Enable[E1=01,01]{NX}@65B
4/INT0 Enable[E1=04,04]{NX}@65B
4/INT1 Enable[E1=08,08]{NX}@65B
4T0 Enable[E1=10,10]{NX}@65B
4T1 Enable[E1=20,20]{NX}@65B
4T2 Enable[E1=40,40]{NX}@65B
4T2EX Enable[E1=80,80]{NX}@65B
4CP0 Enable[E2=01,01]{NX}@65B
4CP1 Enable[E2=02,02]{NX}@65B
4SYSCLK Enable[E2=40,40]{NX}@65B
4SPI Bus Enable[E3=01,01]{NX}@65B
2TITLESelect Pin I/0
3Port 0 Configure
4Bit 0 of Port 0 Push Pull Output[A4=01,01]{NX}@67
4Bit 1 of Port 0 Push Pull Output[A4=02,02]{NX}@67
4Bit 2 of Port 0 Push Pull Output[A4=04,04]{NX}@67
4Bit 3 of Port 0 Push Pull Output[A4=08,08]{NX}@67
4Bit 4 of Port 0 Push Pull Output[A4=10,10]{NX}@67
4Bit 5 of Port 0 Push Pull Output[A4=20,20]{NX}@67
4Bit 6 of Port 0 Push Pull Output[A4=40,40]{NX}@67
4Bit 7 of Port 0 Push Pull Output[A4=80,80]{NX}@67
3Port 1 Configure
4Bit 0 of Port 1 Push Pull Output[A5=01,01]{NX}@67
4Bit 1 of Port 1 Push Pull Output[A5=02,02]{NX}@67
4Bit 2 of Port 1 Push Pull Output[A5=04,04]{NX}@67
4Bit 3 of Port 1 Push Pull Output[A5=08,08]{NX}@67
4Bit 4 of Port 1 Push Pull Output[A5=10,10]{NX}@67
4Bit 5 of Port 1 Push Pull Output[A5=20,20]{NX}@67
4Bit 6 of Port 1 Push Pull Output[A5=40,40]{NX}@67
4Bit 7 of Port 1 Push Pull Output[A5=80,80]{NX}@67
3Port 2 Configure
4Bit 0 of Port 2 Push Pull Output[A6=01,01]{NX}@67
4Bit 1 of Port 2 Push Pull Output[A6=02,02]{NX}@67
4Bit 2 of Port 2 Push Pull Output[A6=04,04]{NX}@67
4Bit 3 of Port 2 Push Pull Output[A6=08,08]{NX}@67
4Bit 4 of Port 2 Push Pull Output[A6=10,10]{NX}@67
4Bit 5 of Port 2 Push Pull Output[A6=20,20]{NX}@67
4Bit 6 of Port 2 Push Pull Output[A6=40,40]{NX}@67
4Bit 7 of Port 2 Push Pull Output[A6=80,80]{NX}@67
3Port 3 Configure
4Bit 0 of Port 3 Push Pull Output[A7=01,01]{NX}@67
4Bit 1 of Port 3 Push Pull Output[A7=02,02]{NX}@67
4Bit 2 of Port 3 Push Pull Output[A7=04,04]{NX}@67
4Bit 3 of Port 3 Push Pull Output[A7=08,08]{NX}@67
4Bit 4 of Port 3 Push Pull Output[A7=10,10]{NX}@67
4Bit 5 of Port 3 Push Pull Output[A7=20,20]{NX}@67
4Bit 6 of Port 3 Push Pull Output[A7=40,40]{NX}@67
4Bit 7 of Port 3 Push Pull Output[A7=80,80]{NX}@67
2TITLEView port pinout
1TITLEComparators
2Comparator 0
3Initially Enabled? [9E=80,80]{NX}@16
3Positive hysterisis?
4Disabled [9E=00,0C]D
4'4.5mV' [9E=04,0C]
4'9mV' [9E=08,0C]
4'17mV' [9E=0C,0C]
3Negative hysterisis?
4Disabled [9E=00,03]D
4'4.5mV' [9E=01,03]
4'9mV' [9E=02,03]
4'17mV' [9E=03,03]
3Comp0 Rising Edge Interrupt Enabled?[E6=20,20]{NX}@15
4Comparator 0 Rising Edge Interrupt Priority High?[F6=20,20]@15
3Comp0 Falling Edge Interrupt Enabled?[E6=10,10]{NX}@15
4Comparator 0 Falling Edge Interrupt Priority High?[F6=10,10]@15
3Enable Comparator 0 as Reset Source?[EF=20,20]{NX}@05
2Comparator 1
3Initially Enabled?[9F=80,80]{NX}@17
3Positive hysterisis?
4Disabled [9F=00,0C]D
4'4.5mV' [9F=04,0C]
4'9mV' [9F=08,0C]
4'17mV' [9F=0C,0C]
3Negative hysterisis?
4Disabled [9F=00,03]D
4'4.5mV' [9F=01,03]
4'9mV' [9F=02,03]
4'17mV' [9F=03,03]
3Comp1 Rising Edge Interrupt Enabled?[E6=80,80]@15
4Comparator 1 Rising Edge Interrupt Priority High?[F6=80,80]@15
3Comp1 Falling Edge Interrupt Enabled?[E6=40,40]@15
4Comparator 1 Falling Edge Interrupt Priority High?[F6=40,40]@15
1TITLEOscillator Configuration
2Internal Oscillator
3Enable Internal Oscillator?[B2=04,04]D{NX}@70
3Select Internal Oscillator typical Frequency Note: Frequency Varies 20%
4'2MHz'[B2=00,03]D@0C
4'4MHz'[B2=01,03]@0D
4'8MHz'[B2=02,03]@0E
4'16MHz'[B2=03,03]@0F
2External Oscillator
3Select External Oscillator Mode to Enable
4Off. XTAL1 pin is grounded internally[B1=00,60]@09
4CMOS Clock on XTAL1 pin Note: XTAL1 is NOT 5V tolerant[B1=20,70]@09
4CMOS Clock on XTAL1 pin with divide by 2 Stage Note: XTAL1 is NOT 5V tolerant[B1=30,70]D@09
5Select Frequency
5'f<=25KHz'[B1=00,07]D@68
5'25KHz<f<=50KHz'[B1=01,07]@68
5'50KHz<f<=100KHz'[B1=02,07]@68
5'100KHz<f<=200KHz'[B1=03,07]@68
5'200KHz<f<=400KHz'[B1=04,07]@68
5'400KHz<f<=800KHz'[B1=05,07]@68
5'800KHz<f<=1.6MHz'[B1=06,07]@68
5'1.6MHz<f<=3.2MHz'[B1=07,07]@68
4C Oscillator Mode with divide by 2 stage Note: frequency is inversely proportional with capacitance for C=100pF frequency is 1/3 of 33pFfor C=100pF frequency is 1/3 of 33pF[B1=40,70]@09
5Select Frequency Assuming C=33pF and AV+=3.3V
5'4.04KHz'[B1=00,07]D@69
5'12.9KHz'[B1=01,07]@69
5'40.40KHz'[B1=02,07]@69
5'119KHz'[B1=03,07]@69
5'349KHz'[B1=04,07]@69
5'918KHz'[B1=05,07]@69
5'3.86MHz'[B1=06,07]@69
5'12.9MHz'[B1=07,07]@69
4Crystal Oscillator Mode[B1=60,70]@09
5Select Frequency
5'f<=12.5kHz[B1=00,07]D@6A
5'12.5kHz<f<=30.3kHz'[B1=01,07]@6A
5'30.35Hz<f<=93.8kHz'[B1=02,07]@6A
5'93.8kHz<f<=267kHz'[B1=03,07]@6A
5'267kHz<f<=722kHz'[B1=04,07]@6A
5'722kHz<f<=2.23MHz'[B1=05,07]@6A
5'2.23MHz<f<=6.74MHz'[B1=06,07]@6A
5'f>=6.74MHz'[B1=07,07]@6A
4Crystal Oscillator Mode with divide by 2 stage[B1=70,70]@09
5Select Frequency
5'f<=12.5kHz[B1=00,07]D@6B
5'12.5kHz<f<=30.3kHz'[B1=01,07]@6B
5'30.35Hz<f<=93.8kHz'[B1=02,07]@6B
5'93.8kHz<f<=267kHz'[B1=03,07]@6B
5'267kHz<f<=722kHz'[B1=04,07]@6B
5'722kHz<f<=2.23MHz'[B1=05,07]@6B
5'2.23MHz<f<=6.74MHz'[B1=06,07]@6B
5'f>=6.74MHz'[B1=07,07]@6B
2Select SYSCLK Source
3Internal Oscillator?[B2=00,08]D
3External Oscillator?[B2=08,08]@63
2Missing Clock Detector
3Enable Missing Clock Detector?[B2=80,80]
1TITLEReference Control Register
2Reference Buffer Control
3VDD VREF[D1=03,03]@5E
3External VREF[D1=00,03]@5D
1TITLESPI Configuration
2SPI Interrupt Enabled?[E6=01,01]{NX}@15
3Set SPI Interrupt Priority High?[F6=01,01]@15
2SPI Clock Phase
3Data sampled on first edge of SCK period?[9A=00,80]D
3Data sampled on second edge of SCK period?[9A=80,80]
2SPI Clock Polarity
3SCK line low in idle state?[9A=00,40]D
3SCK line high in idle state?[9A=40,40]
2Select Mode
3Enable Master Mode?[F8=02,02]@6C
4SPI Frame Size
5'1'[9A=00,07]@6D
5'2'[9A=01,07]@6D
5'3'[9A=02,07]@6D
5'4'[9A=03,07]@6D
5'5'[9A=04,07]@6D
5'6'[9A=05,07]@6D
5'7'[9A=06,07]@6D
5'8'[9A=07,07]D@6D
4SPI Clock Frequency
5Frequency=SYSCLK/2[9A=00,00]@10
5Frequency=SYSCLK/10[9A=00,00]@11
5Frequency=SYSCLK/200[9A=00,00]@12
5Click to Set Custom Frequency[9A=00,00]@13
3Enable Slave Mode?[F8=00,02]D@6C
2Enable SPI?[F8=00,00]{NX}@14
1TITLEUART Configuration
2UART Interrupt Configuration
3Clear UART Recieve and Transmit Interrupt Flags(RECOMMENDED)?[98=00,00]{NX}@28
3Enable Serial Port (UART) Interrupt?[A8=10,10]{NX}@29
4Set Serial Port (UART) Interrupt Priority High?[B8=10,10]@29
2Enable UART Reception?[98=10,10]{NX}
2Select Mode
3 0: Synchronous Mode: Baud Rate=SYSCLK/12[98=00,C0]@6E
3 1: Asynchronous Mode: 8-bit UART, Variable Baud Rate[98=40,C0]@6E
4Use Timer 1 as Baud Rate Source?[88=40,40]@19
5Enable Serial Port Baud Rate Doubler(SMOD=1)?[87=80,80]{NX}
5Timer 1 uses the system clock not divided by 12(T1M=1)[8E=10,10]{NX}@19
5Click to Set 8-bit TH1 reload value{NX}[00=00,00]@18
4Use Timer 2 as Baud Rate Source?[C8=34,34]@27
5Custom RCLK and TCLK settings
6Use Timer 2 overflows for Transmit Clock?[C8=10,10]{NX}@62
6Use Timer 2 overflows for Receive Clock?[C8=20,20]{NX}@62
5Click to set 16-bit RCAP2H:RCAP2L reload value[8E=00,00]{NX}@20
3 2: Asynchronous Mode: 9-bit UART, Fixed Baud Rate[98=80,C0]@6E
4SYSCLK/32?[87=80,80]
4SYSCLK/64?[87=00,80]D
3 3: Asychronous Mode: 9-bit UART,Variable Baud Rate[98=C0,C0]@6E
4Use Timer 1 as Baud Rate Source?[88=40,40]D@19
5Enable Serial Port Baud Rate Doubler(SMOD=1)?[87=80,80]{NX}
5Timer 1 uses system clock not divided by 12(T1M=1)[8E=10,10]{NX}@19
5Click to Set 8-bit TH1 reload value{NX}[00=00,00]@18
4Use Timer 2 as Baud Rate Source?[C8=34,34]@27
5Custom RCLK and TCLK settings
6Timer 2 overflows used for Transmit Clock?[C8=10,10]{NX}
6Timer 2 overflows used for Receive Clock?[C8=20,20]{NX}
5Click to set 16-bit RCAP2H:RCAP2L reload value[8E=00,00]{NX}@20
1TITLETimers Configuration
2Timer 0 and Timer 1
3Timer 0
4Enable Timer 0 Interrupt?[A8=02,02]{NX}@15
5Set Timer 0 Interrpt Priority High?[B8=02,02]@15
4Select Mode
5 13-bit Counter/Timer[89=00,03]D
5 16-bit Counter/Timer[89=01,03]
5 8-bit Counter/Timer[89=02,03]
6Click to Enter 8-bit Reload Value@51
5 Two 8-bit Counter Timers[89=03,03]
4Enable Timer 0?[88=10,10]{NX}
4Gate Timer 0 with /INT0?[89=08,08]{NX}
5Enable /INT0 on the Port I/O MUX?[E1=04,04]@65B
4Timer 0 Event Source
5Timer 0 uses SYSCLK[8E=08,08]
5Timer 0 uses SYSCLK/12[8E=00,08]D
5External T0[89=04,04]
6Enable T0 on the Port I/O MUX?[E1=10,10]@65B
4Click to Enter Timer 0 Inital Value@52
3Timer 1@61
4Enable Timer 1 Interrupt?[A8=08,08]{NX}@15
5Set Timer 1 Interrpt Priority High?[B8=08,08]@15
4Select Mode
5Timer 1 13-bit Counter/Timer Mode[89=00,30]D@62
5Timer 1 16-bit Counter/Timer Mode[89=10,30]@62
5Timer 1 8-bit Counter/Timer Mode[89=20,30]@62
6Click to Enter 8-bit Reload Value@53
5 Timer 1 Inactive OFF[89=30,30]@62
4Enable Timer 1?[88=40,40]{NX}@62
4Gate Timer 1 with INT1?[89=80,80]{NX}
5Enable /INT1 on the Port I/O MUX?[E1=08,08]@65B
4Timer 1 Event Source
5Timer 1 uses SYSCLK[8E=10,10]@62
5Timer 1 uses SYSCLK/12[8E=00,10]D@62
5External T1[89=40,40]@62
6Enable T1 on the Port I/O MUX?[E1=20,20]@65B
4Click to Enter Timer 1 Inital Value@54
2Timer 2@61
3Enable Timer 2 Interrupt?[A8=20,20]{NX}@15
4Set Timer 2 Interrpt Priority High?[B8=20,20]@15
3Select Mode
4 16-bit Capture[C8=0D,3D]
4 16-bit Auto-Reload[C8=04,3D]
5Click to Enter 16-bit Reload Value@55
4 Baud Rate Generator[C8=34,34]@56
5Use Timer 2 overflows for receive clock?[C8=20,20]@56
5Use Timer 2 overflows for transmit clock?[C8=10,10]@56
3Timer 2 Event Source
4Timer 2 uses SYSCLK[8E=20,20]@57
4Timer 2 uses SYSCLK/2 UART Mode[8E=00,00]@57
4Timer 2 uses SYSCLK/12[8E=00,20]@57
4External T2[C8=02,02]{NX}
5Enable T2 on the Port I/O MUX?[E1=40,40]@65B
3Click to Enter Timer 2 16-bit Initial Value@5A
1TITLEReset Source Configuration
2Enable Comparator 0 as a Reset Source?[EF=20,20]{NX}@05
1TITLEInterrupt Configuration
2Enable External /INT0?[A8=01,01]{NX}
3Set External /INT0 Priority to High?[B8=01,01]
2Enable External /INT1?[A8=04,04]{NX}
3Set External /INT1 Priority to High?[B8=04,04]
2Enable External IE4?[E7=04,04]{NX}
3Set External IE4 Priority to High?[F7=04,04]
2Enable External IE5?[E7=08,08]{NX}
3Set External IE5 Priority to High?[F7=08,08]
2Enable External IE6?[E7=10,10]{NX}
3Set External IE6 Priority to High?[F7=10,10]
2Enable External IE7?[E7=20,20]{NX}
3Set External IE7 Priority to High?[F7=20,20]
2Enable SPI Interrupt?[E6=01,01]{NX}@15
3Set SPI Interrupt Priority to High?[F6=01,01]@15
2Comparator 0 Rising Edge Interrupt Enabled?[E6=20,20]{NX}@15
3Set Comparator 0 Rising Edge Interrupt Priority to High?[F6=20,20]@15
2Comparator 0 Falling Edge Interrupt Enabled?[E6=10,10]{NX}@15
3Set Comparator 0 Falling Edge Interrupt Priority to High?[F6=10,10]@15
2Comparator 1 Rising Edge Interrupt Enabled?[E6=80,80]{NX}@15
3Set Comparator 1 Rising Edge Interrupt Priority to High?[F6=80,80]@15
2Comparator 1 Falling Edge Interrupt Enabled?[E6=40,40]{NX}@15
3Set Comparator 1 Falling Edge Interrupt Priority to High?[F6=40,40]@15
2Serial Port (UART) Interrupt Enabled?[A8=10,10]{NX}@29
3Set Serial Port (UART) Interrupt Priority to High?[B8=10,10]@29
2Timer 0 Interrupt Enabled?[A8=02,02]{NX}@15
3Set Timer 0 Interrpt Priority to High?[B8=02,02]@15
2Timer 1 Interrupt Enabled?[A8=08,08]{NX}@15
3Set Timer 1 Interrpt Priority to High?[B8=08,08]@15
2Timer 2 Interrupt Enabled?[A8=20,20]{NX}@15
3Set Timer 2 Interrpt Priority to High?[B8=20,20]@15
2External Clock Source Valid Interrupt Enabled?[E7=80,80]{NX}
3Set External Clock Source Valid Interrupt Priority to High?[F7=80,80]
2Enable Global Interrupts?[A8=80,80]{NX}
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