writebackres.pat

i need of vhdl code for 32-bit risc processor

-- description generated by Pat driver v107
--			date : Sun Dec  2 11:56:57 2001


--		sequence : writeback

-- input / output list :
in       insir5out (15 downto 0) B;
in       alucalval (7 downto 0) B;
in       memoutdata (7 downto 0) B;
in       clock5 B;
in       reset5 B;
out      writebackval (7 downto 0) B;
out      writebackreg (2 downto 0) B;
out      writebackena B;

begin

-- Pattern description :

--                                 i               a       m       cr w        w   w 
--                                 n               l       e       le r        r   r 
--                                 s               u       m       os i        i   i 
--                                 i               c       o       ce t        t   t 
--                                 r               a       u       kt e        e   e 
--                                 5               l       t       55 b        b   b 
--                                 o               v       d          a        a   a 
--                                 u               a       a          c        c   c 
--                                 t               l       t          k        k   k 
--                                                         a          v        r   e 
--                                                                    a        e   n 
--                                                                    l        g   a 

p0                               : 1010000010101000001100110101111100?00110011?010?1;
p1                               : 1010000010101000001100110101111110?00110011?010?1;
-- error on `writebackreg(0)` expected value: -
-- error on `writebackreg(2)` expected value: -
-- error on `writebackval(4)` expected value: +
-- error on `writebackval(7)` expected value: -
p3                               : 0011000111010000111100111010001101?10100011?111?1;
-- error on `writebackreg(0)` expected value: -
-- error on `writebackreg(2)` expected value: -
-- error on `writebackval(7)` expected value: -
-- error on `writebackena` expected value: -
-- error on `writebackreg(1)` expected value: -
-- error on `writebackval(0)` expected value: -
-- error on `writebackval(1)` expected value: -
-- error on `writebackval(5)` expected value: -
p4                               : 0011000111010000111100111010001111?10100011?111?1;

end;