instexec.vst

i need of vhdl code for 32-bit risc processor

ENTITY instexec IS
PORT (
insir3out : IN bit_vector(15 downto 0);
a3outinp : IN bit_vector(7 downto 0);
b3outinp : IN bit_vector(7 downto 0);
imoutinp : IN bit_vector(7 downto 0);
clock3 : IN BIT;
reset3 : IN BIT;
b3regout : OUT bit_vector(7 downto 0);
ir4out : OUT bit_vector(15 downto 0);
aluregout : OUT bit_vector(7 downto 0) 
);
END instexec;

ARCHITECTURE instexec_arch OF instexec IS

COMPONENT alu 
PORT (
al1: IN bit_vector(7 downto 0);
al2: IN bit_vector(7 downto 0);
sel : IN bit_vector(3 downto 0);
alout : OUT bit_vector(7 downto 0)
);
END COMPONENT ;


COMPONENT pc
PORT (
Din2 : IN bit_vector(7 downto 0);
clk2 : IN BIT;
enable2 : IN BIT;
resetpc : IN BIT;
Dout2 : OUT bit_vector(7 downto 0)
);
END COMPONENT ;


COMPONENT instreg 
PORT (
Din1 : IN bit_vector(15 downto 0);
clk1 : IN BIT;
enable1 : IN BIT;
resetir : IN BIT;
Dout1 : OUT bit_vector(15 downto 0)
);
END COMPONENT ;


COMPONENT andgate 
PORT (
a2 : IN BIT;
b2 : IN BIT;
c2 : OUT BIT 
);
END COMPONENT;

COMPONENT bitconv 
PORT (
bit1 : IN BIT;
bit2 : IN BIT;
bit3 : IN BIT;
outvec : OUT bit_vector(2 downto 0)
);
END COMPONENT;

COMPONENT bitconvalu 
PORT (
bit1 : IN BIT;
bit2 : IN BIT;
bit3 : IN BIT;
bit4 : IN BIT;
outvec : OUT bit_vector(3 downto 0)
);
END COMPONENT;

COMPONENT mux2to1
PORT (
inp1 : IN BIT;
inp2 : IN BIT;
en : IN BIT;
outp : OUT BIT
);
END COMPONENT;


COMPONENT notgate
PORT (
a4 : IN BIT;
c4 : OUT BIT
);
END COMPONENT;


COMPONENT buffer1 
PORT (
bu1 : IN BIT;
bu2 : OUT BIT
);
END COMPONENT;

SIGNAL onesig3 : BIT;
SIGNAL zerosig3 : BIT;
SIGNAL branchselect2 : BIT;
SIGNAL selection1 : BIT;
SIGNAL selection2 : BIT;
SIGNAL andvalu1 : BIt;
SIGNAL andvalu2 : BIT;
SIGNAL mux3out : BIT_VECTOR(7 downto 0);
SIGNAL aluregouttemp : BIT_VECTOR(7 downto 0);
--SIGNAL alutemp : BIT_VECTOR(7 downto 0);
--SIGNAL b3temp : BIT_VECTOR(7 downto 0);
SIGNAL b3regouttemp : BIT_VECTOR(7 downto 0);
SIGNAL aluregin : BIT_VECTOR(7 downto 0);
SIGNAL selection : BIT_VECTOR(3 downto 0);

BEGIN

buffer1_3 : buffer1 PORT MAP(clock3,onesig3);

zerosig : notgate PORT MAP(onesig3,zerosig3);

ir4 : instreg PORT MAP(insir3out,clock3,onesig3,reset3,ir4out);

not_3a : notgate PORT MAP(insir3out(14),branchselect2);

--mux to select im or b
mux2to1_3a : mux2to1 PORT MAP(b3outinp(0),imoutinp(0),branchselect2,mux3out(0));
mux2to1_3b : mux2to1 PORT MAP(b3outinp(1),imoutinp(1),branchselect2,mux3out(1));
mux2to1_3c : mux2to1 PORT MAP(b3outinp(2),imoutinp(2),branchselect2,mux3out(2));
mux2to1_3d : mux2to1 PORT MAP(b3outinp(3),imoutinp(3),branchselect2,mux3out(3));
mux2to1_3e : mux2to1 PORT MAP(b3outinp(4),imoutinp(4),branchselect2,mux3out(4));
mux2to1_3f : mux2to1 PORT MAP(b3outinp(5),imoutinp(5),branchselect2,mux3out(5));
mux2to1_3g : mux2to1 PORT MAP(b3outinp(6),imoutinp(6),branchselect2,mux3out(6));
mux2to1_3h : mux2to1 PORT MAP(b3outinp(7),imoutinp(7),branchselect2,mux3out(7));

--changing to bitconvalu
--finding alu function
bitconv3 : bitconvalu PORT MAP(insir3out(9),insir3out(10),insir3out(11),insir3out(12),selection);

alu : alu PORT MAP(a3outinp,mux3out,selection,aluregin);

--selection of values A and B

andgate3_1a : andgate PORT MAP(insir3out(11),insir3out(12),andvalu1);
andgate3_2a : andgate PORT MAP(insir3out(9),insir3out(10),andvalu2);
andgate3_3a : andgate PORT MAP(andvalu1,andvalu2,selection2);

not_3anew : notgate PORT MAP(selection2,selection1);

--here I am chaning mux2to1 PORT MAP(b3outinp(0),aluregin(0),selection1,aluregouttemp(0)); to
--mux2to1 PORT MAP(mux3out(0),aluregin(0),selection1,aluregouttemp(0));


mux3a : mux2to1 PORT MAP(mux3out(0),aluregin(0),selection1,aluregouttemp(0));
mux3b : mux2to1 PORT MAP(mux3out(1),aluregin(1),selection1,aluregouttemp(1));
mux3c : mux2to1 PORT MAP(mux3out(2),aluregin(2),selection1,aluregouttemp(2));
mux3d : mux2to1 PORT MAP(mux3out(3),aluregin(3),selection1,aluregouttemp(3));
mux3e : mux2to1 PORT MAP(mux3out(4),aluregin(4),selection1,aluregouttemp(4));
mux3f : mux2to1 PORT MAP(mux3out(5),aluregin(5),selection1,aluregouttemp(5));
mux3g : mux2to1 PORT MAP(mux3out(6),aluregin(6),selection1,aluregouttemp(6));
mux3h : mux2to1 PORT MAP(mux3out(7),aluregin(7),selection1,aluregouttemp(7));


mux4a : mux2to1 PORT MAP(mux3out(0),aluregin(0),selection2,b3regouttemp(0));
mux4b : mux2to1 PORT MAP(mux3out(1),aluregin(1),selection2,b3regouttemp(1));
mux4c : mux2to1 PORT MAP(mux3out(2),aluregin(2),selection2,b3regouttemp(2));
mux4d : mux2to1 PORT MAP(mux3out(3),aluregin(3),selection2,b3regouttemp(3));
mux4e : mux2to1 PORT MAP(mux3out(4),aluregin(4),selection2,b3regouttemp(4));
mux4f : mux2to1 PORT MAP(mux3out(5),aluregin(5),selection2,b3regouttemp(5));
mux4g : mux2to1 PORT MAP(mux3out(6),aluregin(6),selection2,b3regouttemp(6));
mux4h : mux2to1 PORT MAP(mux3out(7),aluregin(7),selection2,b3regouttemp(7));

alu4reg : pc PORT MAP(aluregouttemp,clock3,onesig3,reset3,aluregout);

bval : pc PORT MAP(b3regouttemp,clock3,onesig3,reset3,b3regout);

END;