memaccess.vst

i need of vhdl code for 32-bit risc processor

ENTITY memaccess IS
PORT (
insir4out : IN bit_vector(15 downto 0);
datafake : IN bit_vector(7 downto 0); 
alureginp : IN bit_vector(7 downto 0); 
b4outinp : IN bit_vector(7 downto 0);
clock4 : IN BIT;
reset4 : IN BIT;
ir5out : OUT bit_vector(15 downto 0); 
alucalout : OUT bit_vector(7 downto 0); 
datamemout : OUT bit_vector(7 downto 0);
memwriteenable : OUT BIT
);
END memaccess;


ARCHITECTURE memaccess_arch OF memaccess IS

COMPONENT datamem 
PORT (
alucalc : IN bit_vector(7 downto 0);
databinp : IN bit_vector(7 downto 0); 
fakedata : IN bit_vector(7 downto 0); 
clk4 : IN BIT; 
en : IN BIT;
aluvalue : OUT bit_vector(7 downto 0);
memout : OUT bit_vector(7 downto 0);
datawritten :  OUT bit_vector(7 downto 0)
);
END COMPONENT;

COMPONENT instreg 
PORT (
Din1 : IN bit_vector(15 downto 0);
clk1 : IN BIT;
enable1 : IN BIT;
resetir : IN BIT;
Dout1 : OUT bit_vector(15 downto 0)
);
END COMPONENT ;


COMPONENT pc
PORT (
Din2 : IN bit_vector(7 downto 0);
clk2 : IN BIT;
enable2 : IN BIT;
resetpc : IN BIT;
Dout2 : OUT bit_vector(7 downto 0)
);
END COMPONENT ;


COMPONENT buffer1 
PORT (
bu1 : IN BIT;
bu2 : OUT BIT
);
END COMPONENT;


COMPONENT andgate 
PORT (
a2 : IN BIT;
b2 : IN BIT;
c2 : OUT BIT 
);
END COMPONENT;

--COMPONENT forwardtoir
--PORT (
--inputvectorir : IN bit_vector(15 downto 0);
--outputvectorir : OUT bit_vector(15 downto 0)
--);
--END COMPONENT;

SIGNAL onesig4 : BIT;
SIGNAL writedata : BIT_VECTOR(7 downto 0);
SIGNAL alucalouttemp : BIT_VECTOR(7 downto 0);
SIGNAL datamemouttemp : BIT_VECTOR(7 downto 0);
SIGNAL andval1 : BIT;
SIGNAL andval2 : BIT;



BEGIN


buffer1_4 : buffer1 PORT MAP(clock4,onesig4);

datamem : datamem PORT MAP(alureginp,b4outinp,datafake,clock4,onesig4,alucalouttemp,datamemouttemp,writedata);

pc4_1 : pc PORT MAP(alucalouttemp,clock4,onesig4,reset4,alucalout);
pc4_2 : pc PORT MAP(datamemouttemp,clock4,onesig4,reset4,datamemout);

ir5 : instreg PORT MAP(insir4out,clock4,onesig4,reset4,ir5out);
--fwdtoout : forwardtoir PORT MAP(insir4out,ir5out);
--enable output
andgate3_1 : andgate PORT MAP(insir4out(11),insir4out(12),andval1);
andgate3_2 : andgate PORT MAP(insir4out(9),insir4out(10),andval2);
andgate3_3 : andgate PORT MAP(andval1,andval2,memwriteenable);

end;