designer.log

主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程

Actel Designer Software
Version: 8.3.0.22
Release: v8.3


 Netlist Reading Time = 0.0 seconds
Imported the files:
   E:\programer_new\UART\project\synthesis\uart_test.edn
   E:\programer_new\UART\project\synthesis\uart_test_sdc.sdc

The Import command succeeded ( 00:00:06 )
The design E:\programer_new\UART\project\designer\impl1\uart_test.adb was last modified by
software version 8.3.0.22.
Opened an existing Libero design E:\programer_new\UART\project\designer\impl1\uart_test.adb.
'BA_NAME' set to 'uart_test_ba'

The Execute Script command succeeded ( 00:00:00 )
=====================================================================
Parameters used to run compile:
===============================

Family      : ProASIC3
Device      : A3P030
Package     : 100 VQFP
Source      : E:\programer_new\UART\project\synthesis\uart_test.edn
              E:\programer_new\UART\project\synthesis\uart_test_sdc.sdc
Format      : EDIF
Topcell     : uart_test
Speed grade : -2
Temp        : 0:25:70
Voltage     : 1.58:1.50:1.42

Keep Existing Physical Constraints : Yes
Keep Existing Timing Constraints   : Yes

pdc_abort_on_error                 : Yes
pdc_eco_display_unmatched_objects  : No
pdc_eco_max_warnings               : 10000

demote_globals                     : No
promote_globals                    : No
localclock_max_shared_instances    : 12
localclock_buffer_tree_max_fanout  : 12

combine_register                   : No
delete_buffer_tree                 : No

report_high_fanout_nets_limit      : 10

=====================================================================
Compile starts ...


Netlist Optimization Report
===========================

Optimized macros:
  - Dangling net drivers:   0
  - Buffers:                0
  - Inverters:              0
  - Tieoff:                 0
  - Logic combining:        4

    Total macros optimized  4

There were 0 error(s) and 0 warning(s) in this design.
=====================================================================

Reading previous post-compile physical placement constraints.


There were 0 error(s) and 0 warning(s).

=====================================================================
Compile report:
===============

    CORE                     Used:    260  Total:    768   (33.85%)
    IO (W/ clocks)           Used:      3  Total:     77   (3.90%)
    GLOBAL (Chip)            Used:      1  Total:      6   (16.67%)
    Low Static ICC           Used:      0  Total:      1   (0.00%)
    FlashROM                 Used:      0  Total:      1   (0.00%)
    User JTAG                Used:      0  Total:      1   (0.00%)

Global Information:

    Type            | Used   | Total
    ----------------|--------|-------------
    Chip global     | 1      | 6  (16.67%)

Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 179          | 179
    SEQ     | 81           | 81

I/O Function:

    Type                          | w/o register  | w/ register  | w/ DDR register
    ------------------------------|---------------|--------------|----------------
    Input I/O                     | 2             | 0            | 0
    Output I/O                    | 1             | 0            | 0
    Bidirectional I/O             | 0             | 0            | 0
    Differential Input I/O Pairs  | 0             | 0            | 0
    Differential Output I/O Pairs | 0             | 0            | 0

I/O Technology:

                                    |   Voltages    |             I/Os
    --------------------------------|-------|-------|-------|--------|--------------
    I/O Standard(s)                 | Vcci  | Vref  | Input | Output | Bidirectional
    --------------------------------|-------|-------|-------|--------|--------------
    LVTTL                           | 3.30v | N/A   | 2     | 1      | 0

Net information report:
=======================

The following nets have been assigned to a chip global resource:
    Fanout  Type          Name
    --------------------------
    70      CLK_NET       Net   : clock_c
                          Driver: clock_pad
                          Source: NETLIST

High fanout nets in the post compile netlist:
    Fanout  Type          Name
    --------------------------
    12      INT_NET       Net   : uartrec/StartF
                          Driver: uartrec/StartF
    12      INT_NET       Net   : uartrec/clkrec
                          Driver: uartrec/clkout
    11      INT_NET       Net   : clkout
                          Driver: uartsend/clkout_0_a3
    10      INT_NET       Net   : WR
                          Driver: WR
    10      INT_NET       Net   : uartrec/count_bit_2_sqmuxa
                          Driver: uartrec/bit_collect_0_e[2]
    10      INT_NET       Net   : uartsend/clksend_0
                          Driver: uartsend/clkout_inferred_clock_0
    9       CLK_NET       Net   : RI
                          Driver: uartrec/RI
    9       INT_NET       Net   : uartrec/bit4
                          Driver: uartrec/bit4
    8       INT_NET       Net   : uartsend/bincnt[0]
                          Driver: uartsend/bincnt[0]
    8       INT_NET       Net   : uartsend/N_51
                          Driver: uartsend/cnt_n8_i_o3

Nets that are candidates for clock assignment and the resulting fanout:
    Fanout  Type          Name
    --------------------------
    20      INT_NET       Net   : clkout
                          Driver: uartsend/clkout_0_a3
    12      INT_NET       Net   : uartrec/StartF
                          Driver: uartrec/StartF
    12      INT_NET       Net   : uartrec/clkrec
                          Driver: uartrec/clkout
    10      INT_NET       Net   : WR
                          Driver: WR
    10      INT_NET       Net   : uartrec/count_bit_2_sqmuxa
                          Driver: uartrec/bit_collect_0_e[2]
    9       CLK_NET       Net   : RI
                          Driver: uartrec/RI
    9       INT_NET       Net   : uartrec/bit4
                          Driver: uartrec/bit4
    8       INT_NET       Net   : uartsend/bincnt[0]
                          Driver: uartsend/bincnt[0]
    8       INT_NET       Net   : uartsend/N_51
                          Driver: uartsend/cnt_n8_i_o3
    7       INT_NET       Net   : RXD_c
                          Driver: RXD_pad


SDC Import: Begin processing constraints...



SDC Import: End processing constraints


The Compile command succeeded ( 00:00:05 )
I/O Bank Assigner detected (2) out of (2) I/O Bank(s) with locked I/O technologies.
I/O Bank Assigner is running in incremental mode. All pre-assigned I/O Bank technologies will
not be changed.
All I/O Banks have locked technologies. Skipping I/O Bank Assigner.

Planning global net placement...

Global net placement completed successfully.

                        o - o - o - o - o - o

Timing-driven Placer Started: Tue Aug 19 09:09:40 2008

Placer Finished: Tue Aug 19 09:09:42 2008
Total Placer CPU Time:     00:00:02

                        o - o - o - o - o - o

INFO: NO_TOP_AGGREGATION option enabled
INFO: Writing the file: E:\programer_new\UART\project\designer\impl1\uart_test.dtf\swloc

Timing-driven Router 
Design: uart_test                       Started: Tue Aug 19 09:09:45 2008

14 nets of 263 have to be routed incrementally.
 

Timing-driven Router completed successfully.

Design: uart_test                       
Finished: Tue Aug 19 09:09:47 2008
Total CPU Time:     00:00:01            Total Elapsed Time: 00:00:02
                        o - o - o - o - o - o

Loading the Timing data for the design.
Finished loading the Timing data.
TIMER: Max delay timing requirements have been met.

The Layout command succeeded ( 00:00:13 )

Running I/O Bank Assigner.

I/O Bank Assigner completed successfully.
 

Planning global net placement...

Global net placement completed successfully.

                        o - o - o - o - o - o

Timing-driven Placer Started: Tue Aug 19 09:10:11 2008

Placer Finished: Tue Aug 19 09:10:19 2008
Total Placer CPU Time:     00:00:08

                        o - o - o - o - o - o

INFO: NO_TOP_AGGREGATION option enabled

Timing-driven Router 
Design: uart_test                       Started: Tue Aug 19 09:10:21 2008

 
Iterative improvement...

Timing-driven Router completed successfully.

Design: uart_test                       
Finished: Tue Aug 19 09:10:31 2008
Total CPU Time:     00:00:09            Total Elapsed Time: 00:00:10
                        o - o - o - o - o - o

Loading the Timing data for the design.
Finished loading the Timing data.
TIMER: Max delay timing requirements have been met.

The Layout command succeeded ( 00:00:24 )
Warning: The following files already exist:
         
         E:\programer_new\UART\project\designer\impl1\uart_test.pdb
         
         Do you want to replace the files? [YES]
INFO: NO_TOP_AGGREGATION option enabled

The Export-map command succeeded ( 00:00:06 )
Warning: Overwriting the existing file:
         E:\programer_new\UART\project\designer\impl1\uart_test.pdb.
Wrote to the file: E:\programer_new\UART\project\designer\impl1\uart_test.pdb
CHECKSUM: 1242

The Generate programming file command succeeded ( 00:00:07 )
Design saved to file E:\programer_new\UART\project\designer\impl1\uart_test.adb.
Design closed.