verify.log

来自「主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程」· LOG 代码 · 共 9 行

cdlver completed successfully.

Design:                                 
Finished: Tue Aug 19 09:10:51 2008
Total CPU Time:     00:00:03            Total Elapsed Time: 00:00:04
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