verify.log

主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程

cdlver completed successfully.

Design:                                 
Finished: Tue Aug 19 09:10:51 2008
Total CPU Time:     00:00:03            Total Elapsed Time: 00:00:04
                        o - o - o - o - o - o